Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Massively parallel architectures for handling large designs and supporting multi-threading on multi-core workstations, as well as distributed processing over networks of computers
- New GigaPlace™ solver-based placement technology, which is slack-driven and topology-, pin access- and color-aware to provide optimal pipeline placement, wire length, utilization, and PPA
- Advanced, multi-threaded, layer-aware optimization engine that is timing- and power-driven to reduce dynamic and leakage power
Cadence® Innovus™ Implementation System is optimized for industry-leading embedded processors, as well as for 16nm, 14nm, and 10nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus Implementation System features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you’ll need to get to market faster. Using the Innovus Implementation System, you’ll be equipped to build integrated, differentiated systems with less risk.
The implementation system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.
Next-generation slack-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The implementation system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity.
Cadence’s Tempus™ static timing analysis, Quantus™ parasitic extraction, and Voltus™ power integrity technologies are integrated with Innovus Implementation System. With this integration, you can accurately model the parasitics, timing, signal, and power integrity issues at the early stage of physical implementation and achieve faster convergence on these electrical metrics, resulting in faster design closure.
Our products enable the reception of broadband data and video content, requiring high levels of performance, small silicon die-size, and rapid time to market. Innovus Implementation System has provided us with unprecedented full-flow speed-up, so we can deliver reliable designs to market faster.
Dr. Paolo Miliozzi, Senior Director, SOC Technology and Physical Design, MaxLinear
We've tested the full Innovus Implementation System flow on some of our most congestion-challenged 28nm networking IP blocks and have achieved excellent results while seeing significant throughput improvements. The new Cadence solution has enabled us to resolve our most difficult timing requirements…
Fares Bagh, Vice President, Hardware and Architecture Engineering in Freescale's Digital Networking Group
Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.
Debashis Basu, SVP Engineering, Silicon and Systems Engineering, Juniper Networks
Innovus Implementation System provided us with substantial gains in quality of results and speed-up for our most challenging design.
Tatsuji Kagatani, Dept. Manager, Design Automation Dept., Elemental Technology Development Division at Renesas System Design Co., Ltd.
At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets. We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement…
Noel Hurley, General Manager, CPU Group, ARM
The Innovus Implementation System significantly improved the runtime on a critical multi-million-cell IP core compared to our previous solution. With runtimes improved to deliver more than a million cells per day of implementation throughput, we can confidently drive our aggressive schedules…
Robin Lu, Vice President of ASIC, Spreadtrum Communications