Overview
One-Stop Shop: Proven Design Flows for Multi-Chiplet Design and Advanced IC Packaging
The Cadence 3D-IC solution provides 3D design planning, implementation, and system analysis in a single, unified cockpit. It enables hardware and software co-verification and full-system power analysis using emulation and prototyping and chiplet-based PHY IP for connectivity with power, performance, and area (PPA) optimized for latency, bandwidth, and power. The solution also offers co-design capabilities with custom analog design and board design, integrated circuit (IC) signoff extraction, static timing analysis (STA) and signoff with signal and power integrity (SI/PI), electromagnetic interference (EMI), and thermal analysis.
Key Benefits
Advantages of Designing with Solutions from the 3D-IC Experts
With more than 25 years of advanced packaging experience, we enable our customers to generate higher bandwidth, lower power consumption, and reduce area without traditional process scaling.
Heterogeneous Integration
Allows heterogeneous integration of different dies for 2.5D or 3D designs
Performance and Power
System-driven PPA for best power efficiency without compromising performance
Maximum Functionality
Support for numerous applications in AI, data center, graphics, and mobile communications ICs with a smaller form factor
Offerings
Addressing the Requirements of 3D-IC Design for Digital SoCs, Analog/Mixed-Signal Designs, and Entire Systems
Multi-Chiplet Planning and Implementation
The Cadence Integrity 3D-IC Platform is a high-capacity, unified design and analysis platform for designing multiple chiplets. Built on the infrastructure of Cadence’s leading digital implementation solution, the Innovus Implementation System, the platform allows system-level designers to plan, implement, and analyze any type of stacked die system for a variety of packaging styles (2.5D or 3D). Integrity 3D-IC is the industry’s first integrated system- and SoC-level solution that enables system analysis, including co-design, with Cadence’s Virtuoso and Allegro analog and package implementation environments.
Die/Package Planning and Route Optimization
To efficiently plan and assess connectivity and route feasibility in your 3D-IC design, look to the Cadence Integrity System Planner. Quickly evaluate the connectivity between the die and package in the context of your full system. Make or refine decisions, then immediately visualize the impact on adjacent fabrics within this single tool to cut down on iterations between silicon and package design teams.
Logic Die DFT
When ready to test, look to the Cadence Genus Synthesis Solution and Cadence Modus DFT Software products for logic die design for test (DFT). Using these tools, perform a DFT insertion to test the die-to-die interconnect, including silicon interposers.
Electrical Signoff and System Analysis
In the analysis and signoff phase, you’ll need to validate your design, ensuring that the inter-die in your 3D implementation is correct. You can use the Cadence Pegasus Verification System to perform a cross-die check. You’ll also need to evaluate electrical performance. On the digital side, we offer an array of tools for extraction and timing and power signoff.
The Cadence Quantus Extraction Solution provides parasitic extraction and analysis for TSVs, micro-bumps, and other characteristics associated with 3D technologies.
The Cadence Tempus Timing Signoff Solution provides silicon-accurate timing signoff and signal integrity analysis across multiple dies.
The Cadence Clarity 3D Solver models and performs 3D electromagnetic simulation of high-speed interconnects for PCBs, IC packages, and System-on-Chip (SoC). For PCB and IC packages, Cadence's Sigrity technology provides high-speed system designers with the most comprehensive end-to-end in-design interconnect modeling as well as signal and power integrity (SI/PI) simulation.
Thermal Management
The Cadence 3D-IC solution offers a unique capability for thermal management of 3D-IC designs. The Cadence Voltus IC Power Integrity Solution generates thermal models that are fed into the Celsius Thermal Solver, which uses this data to determine the temperature distribution for each die. The Celsius Thermal Solver feeds back a temperature map to the Voltus solution for temperature-dependent multi-die IR drop analysis. If you need to run thermal analysis through many iterations, the Voltus solution's GUI allows you to invoke the thermal engine within the solution to get the temperature results automatically displayed at the die level.
Multi-Die Physical Verification
The Cadence Pegasus Verification System is a cloud-ready physical verification signoff solution that enables engineers to deliver advanced-node ICs to market faster. The groundbreaking technology delivers up to 10X improved design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours. The Pegasus system’s innovative architecture and integrated cloud processing provide an elastic and flexible computing environment, which enables customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market faster.
Hardware/Software Validation and Power Analysis
The Cadence Palladium Z2 Enterprise Emulation Platform offers scalability of up to 10B gates on multi-chiplet system designs with power analysis and optimization.
Chiplet-Based IP
Cadence offers chiplet-based PHY IP optimized for latency, bandwidth, and power. Our UltraLink D2D IP supports speeds of up to 40Gbps with 1TB/mm efficiency and includes a complementary controller and management stack. Additionally, our UCIe IP supports speeds up to 32Gbps, providing a robust die-to-die interface between chiplets. It seamlessly handles industry-standard interconnects like PCI Express (PCIe) and Compute Express Link (CXL), ensuring high performance and reliability.
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