Custom IC / Analog / Microwave & RF Design Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
Circuit Design and Simulation
- Analog Modeling and Simulation with SPICE
- Design Checks and Asserts
- High-Performance Spectre Simulation
- Simulation and Analysis Using OCEAN
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Variation Analysis Using the Virtuoso Variation Option
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Schematic Editor
- Virtuoso Spectre Pro S1: DC Algorithm
- Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
- Virtuoso Spectre Pro S2: Transient Algorithm
- Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
- Virtuoso Spectre Pro S5: Transient Noise
- Virtuoso System Design Platform
- Virtuoso Visualization and Analysis
Mixed-Signal Modeling and Simulation
- Analog Modeling with Verilog-A
- Behavioral Modeling with Verilog-AMS
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using Spectre AMS Designer
- Real Modeling with SystemVerilog
- Real Modeling with Verilog-AMS
- SimVision for Debugging Mixed-Signal Simulations
- SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
Physical Design
- Pegasus Verification System
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- SKILL Language Programming Introduction
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
- Virtuoso Layout Pro: T2 Create and Edit Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T5 Interactive Routing (XL)
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Advanced Nodes and Methodology Platform
- Virtuoso Simulation Driven Routing (SDR)
