Custom IC / Analog / Microwave & RF Design Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
Circuit Design and Simulation
- Analog Circuit Design and Simulation Onboarding
- Analog Modeling and Simulation with SPICE
- Analyzing Simulation Results Using Virtuoso Visualization and Analysis
- Design Checks and Asserts in Spectre Simulator
- Electromagnetic Simulations Using the EMX Solver
- FastSpice Simulations Using Spectre FX Simulator
- Getting the Best Spectre Simulator Results with Andrew Beckett
- High-Performance Spectre Simulation
- Reliability Analysis in Virtuoso Studio
- Spectre FMC in Virtuoso ADE
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Using Spectre Effectively S1: Accelerating DC Analysis
- Using Spectre Effectively S2: Accelerating Transient Analysis
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Heterogeneous Integration: EM Analysis of ICs Using the EMX Solver
- Virtuoso Schematic Editor
- Virtuoso Spectre Transient Noise
- Virtuoso System Design Platform
Physical Design
- Boost Your Layout Productivity with Virtuoso Studio
- Cadence Analog IC Design Flow
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T1 Environment and Basic Commands
- Virtuoso Layout Pro: T2 Create and Edit Commands
- Virtuoso Layout Pro: T3 Basic Commands
- Virtuoso Layout Pro: T4 Advanced Commands
- Virtuoso Layout Pro: T5 Interactive Routing
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner
- Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Photonics Design - T1
- Virtuoso Studio Features
Physical Verification
- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T4 Advanced Commands