Chip and system design for data centers push the limits of today’s capabilities in the areas of chip-design, hardware/software co-development, board development, and system analysis. Optimization for individual computing workloads requires flexibility to include domain-specific accelerators and to create multiple derivatives and design options with as little lead time as possible. Also, design complexities today extend beyond the current reticle limits for yield-efficient manufacturing. The assembly of chiplets has emerged as the solution.
Explore how Cadence’s integrated 3D-IC assembly offerings create fast derivatives of disaggregated systems on chip (SoCs). See how our integrated design tools, combined with Cadence design and processor IP, enable designs optimized for low power, thermal effects, and energy consumption, an essential requirement for hyperscaled data centers. Learn how to use emulation, prototyping, and metric-driven verification to optimize hardware/software interaction and shift-left software development. Experience the flows for AI/ML designs, which provide everything from silicon IP and high-level synthesis to high-capacity verification and AI/ML-optimized implementation and system assembly.
Some of the key system architecture decisions in the era of hyperscale computing revolve around computing and storage. Depending on latency requirements dictated by the applications under development, compute may happen at the sensors, on mobile devices, in near- or far-edge nodes, or in local and cloud data centers. Low-power, energy, and thermal requirements may require compute to be offloaded from mobile devices. These decisions are highly application-dependent and require a keen understanding of the data journey—from sensing to actionable AI/ML-driven decisions/insights that impact our day-to-day lives.
Explore how Cadence’s emulation, verification, and FPGA-based prototyping offerings allow early software development for mobile and edge devices, providing the performance assessments required for specific compute workloads. Learn how edge-optimized, extendible processor and design IP accelerates product development and lets design teams achieve the most energy-optimized hardware/software implementations. See how the integrated Cadence design flows across verification, digital and custom implementation, and system analysis enable low-power-, energy-, and thermal-optimized domain-specific products.
Wired and wireless networks are the backbone that allows data to seamlessly flow through hyperscaled networks, with 5G providing next-generation wireless networks and faster and faster Ethernet and optical connections to build wired connections.
Discover how Cadence products enable 5G RF module designs for handsets, making use of the very large bandwidth offered by millimeter wave (mmWave), and how co-design of RFIC, package, and modules allow design teams to more quickly design smaller, lower power devices that are optimized using system-level thermal and electromagnetic (EM) analysis. Explore how Cadence design tools can help you meet high-frequency and beamforming requirements for 5G radioheads. Learn about Cadence’s integrated silicon photonic and electronic co-design for optical transceivers and 100G Ethernet IP support for complicated 5G fronthaul connectivity to multiple radioheads.