The Cadence® AWR Design Environment® platform provides RF/microwave engineers with integrated high-frequency circuit (Cadence AWR® Microwave Office® software), system (Cadence AWR Visual System Simulator™ (VSS) software), and electromagnetic (EM) (Cadence AWR AXIEM analysis/Cadence AWR Analyst software) simulation technologies and design automation to develop physically realizable electronics ready for manufacturing. The platform helps designers manage complex IC, package, and PCB modeling, simulation, and verification, addressing all aspects of circuit behavior to achieve optimal performance and reliable results for first-pass success.
A powerful and intuitive user interface ensures optimal engineering productivity with smart, customizable design flows for today's high-frequency semiconductor and PCB technologies
System, circuit, and EM simulation technologies are integrated for fast and accurate analysis of device performance prior to prototype manufacturing and test, saving development time and costs
Design-flow automation connects simulation models, third-party tools, and layout to manufacturing processes, from early concept exploration through to engineering signoff
Provides front-to-back physical design flow with dynamically linked electrical and layout design entry. Components placed in an electrical schematic automatically generate a synchronized physical layout based on libraries of standard, customized, and/or vendor-provided components.
Integrates circuit, system, and EM simulation technologies for investigating linear and nonlinear network behavior. Designers can perform in-situ EM extraction of interconnects, develop component specifications from system link budgets, and analyze device performance with system testbenches for communication standards.
Supports complex hierarchical projects with parameterized subcircuits for easy optimization and tuning. Circuit, system, or EM-based subcircuits can be quickly developed and used to populate larger, more complex networks common in today’s RF front-end circuitry.
Third-party interoperability with industry-standard tools enables the exchange of design data for schematic or netlist import, bi-directional EM co-simulation, electrical-rule check (ERC)/design-rule check (DRC)/layout vs. schematic (LVS), and production-ready GDSII export. Additionally, powerful yield analysis and optimization addresses manufacturing tolerances for more robust designs and greater profitability.
The powerful application programming interface (API) extends the capabilities of the software using popular programming languages, providing user-defined scripts for automating common or complex tasks and custom design flows.