IC Package Design and
Analysis

Driving accuracy in advanced packaging and cross-domain interoperability

Key Benefits

Chip / Package Co-Design

Create higher performing, lower cost packages

Multi-Chip(let) Design

Robust support for multi-chip(let) heterogeneously integrated designs

Comprehensive Design

Analysis and verification flow for fan-out wafer-level package (FOWLP)

Reference Flows

Support for major foundry and OSAT advanced packaging

Product Catagories

IC Package Design

Constraint-driven correct-by-construction package substrate layout

Cross-Platform Co-Design and Analysis

Direct integration with Virtuoso® and Innovus™ IC flows

Multi-Chip(let) Design

Complete front-to-back design-through-verification flow

SI/PI Analysis

Advanced integrated PI and power-aware SI tools to ensure better design performance

SI/PI Analysis Point Tools

Signal integrity analysis with signoff-level accuracy

Solutions

Cross-Platform

Cross-platform interconnects unify IC, package, and PCB data to easily derive and evaluate signal-to-bump/ball-assignment and connectivity/routing-pathway scenarios

3D-IC

Our 3D-IC solution reduces power, raises performance, and enables maximum functionality in a smaller form factor

FOWLP

Our FOWLP flow shortens your design and verification cycle and increases system bandwidth while decreasing power consumption

Cross-Platform/Cross-Domain Multi-Chip(let)

Our cross-platform/cross-domain multi-chip(let) packaging flow provides a unified “system-aware” platform for concurrent design across chip, package, and board

Resources

White Paper

Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, PCBs, and Packages

Press Release

Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology

Press Release

Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology

Video

Resolving Common IC Package Electrical Concerns

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News ReleasesVIEW ALL

Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

Cadence Presented with Four 2019 TSMC Partner of the Year Awards 10/30/2019

Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology 10/17/2019

Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES 02/14/2019