Key Benefits
Chip / Package Co-Design
Create higher performing, lower cost packages
Multi-Chip(let) Design
Robust support for multi-chip(let) heterogeneously integrated designs
Comprehensive Design
Analysis and verification flow for fan-out wafer-level package (FOWLP)
Reference Flows
Support for major foundry and OSAT advanced packaging
Resources
Press Release
Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology
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Press Release
Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
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Video
Resolving Common IC Package Electrical Concerns
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