Key Benefits

Chip / Package Co-Design

Create higher performing, lower cost packages

Multi-Chip(let) Design

Robust support for multi-chip(let) heterogeneously integrated designs

Comprehensive Design

Analysis and verification flow for fan-out wafer-level package (FOWLP)

Reference Flows

Support for major foundry and OSAT advanced packaging

Product Catagories

IC Package Design

Constraint-driven correct-by-construction package substrate layout

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Cross-Platform Co-Design and Analysis

Direct integration with Virtuoso® and Innovus™ IC flows

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Multi-Chip(let) Design

Complete front-to-back design-through-verification flow

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SI/PI Analysis

Advanced integrated PI and power-aware SI tools to ensure better design performance

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SI/PI Analysis Point Tools

Signal integrity analysis with signoff-level accuracy

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Solutions

Cross-Platform

Cross-platform interconnects unify IC, package, and PCB data to easily derive and evaluate signal-to-bump/ball-assignment and connectivity/routing-pathway scenarios

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3D-IC

Our 3D-IC solution reduces power, raises performance, and enables maximum functionality in a smaller form factor

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FOWLP

Our FOWLP flow shortens your design and verification cycle and increases system bandwidth while decreasing power consumption

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Cross-Platform/Cross-Domain Multi-Chip(let)

Our cross-platform/cross-domain multi-chip(let) packaging flow provides a unified “system-aware” platform for concurrent design across chip, package, and board

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Resources