Run More Validation Cycles on Bigger Chips in Less Time
Our dynamic duo meets today’s requirements for pre-silicon verification of advanced SoC designs as two tightly integrated systems, Cadence® Palladium™ Z2 Enterprise Emulation, optimized for rapid predictable hardware debug, and Cadence Protium™ X2 Enterprise Prototyping, optimized for highest performance multi-billion gate software validation.
Cadence Dynamic Duo Advantage
The Right Tool, for the Right Job, at the Right Time
Portfolio of Products
Designs and software are growing in complexity. Cadence provides a comprehensive solution for IP and SoC verification, hardware and software regressions, and early software development.
Our newest prototyping platform, the Protium X2 system, offers the highest performance and fastest bring-up times for pre-silicon software validation of billion gate designs.
Verified with Cadence
Learn how our customers use the Dynamic Duo to optimize workload distribution between verification, validation and pre-silicon software bring-up and adopt a shift-left methodology to accelerate their product development process.
AMD Designs 3rd-Gen EPYC Server Processors for HPC with Dynamic Duo
Palladium and Protium help AMD push emulation in capacity, next-gen testbench design, advanced clocking, and hybrid use.
With twice the useable capacity, 50 percent higher throughput, and faster modular compiler turnaround, we can validate our most sophisticated GPU and SoC designs comprehensively and on schedule.
Narendra Konda, Senior Director, Hardware Engineering, NVIDIA Corporation
The ability to perform design bring-up and transition between the Palladium Z2 emulation and the Protium X2 prototyping platforms in short time provides us with the opportunity to optimize our shift-left deployment for our most challenging SoC designs.
Alex Starr, Corporate Fellow, Methodology Architect, AMD
Best-in-class emulations are key to our success, and Arm uses emulation extensively together with simulation on Arm-based servers to achieve the highest verification throughput.
Tran Nguyen, Senior Director, Design Services, Arm
The tightly integrated Cadence and Xilinx front-to-back flow allows software developers to use the platform at the earliest possible point during the development flow and to focus on design validation and software development rather than prototype bring-up.
Hanneke Krekels, Senior Director, Core Vertical Markets, Xilinx, Inc