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Video (10)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- 应用iSpatial流程达到卓越设计: 工欲善其事,必先利其器
- Pushing frequency, power and area with the iSpatial flow to achieve Design Excellence
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- Maximizing PPA on ARM’s Next-Generation High-Performance Processor Using the Latest Cadence Implementation and Signoff Tools/Flow
- Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership
- eInfochips Shortens Runtime on 300M Gate Count SoCs with Innovus Implementation System
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Demo Videos (5)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Press Releases (5)
- Cadence 推出革命性新产品Cerebrus——完全基于机器学习 ,提供一流生产力和结果质量,拓展数字设计领导地位
- Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
- Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
- Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology
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