Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement Innovation
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Key Benefits
- 大规模并行架构，用于处理大型设计，支持多核工作站上的多线程功能以及计算机网络上的分布式处理
- 基于求解器的全新 GigaPlace 摆放技术，依据时序、功率和拥塞数据，通过了解对拓扑、引脚连接和颜色的感知，提供最优化的单元摆放、线长、利用率和 PPA 结果
- 独特的混合宏和标准单元摆放功能可实现自动宏定位，以适应越来越复杂的平面分布图（包含数百个宏单元）
- 先进的 GigaOpt 多线程、可感知金属层的优化引擎，该引擎依据时序和功率数据，可降低动态功耗和漏电功耗
- 其他高级节点技术，例如通孔支柱、可感知电源完整性的单元摆放和优化、功耗时钟偏斜、连续拥塞监控，以及用于处理自对准双图案的、经过优化的布线器，以实现更好的 PPA 结果
- 适用于大型分层设计的成熟分层自动化功能，例如高级模块抽取、自动分区和分层时序收敛，以及新的平面图综合功能
- 基于机器学习的创新功能贯穿整个实施流程，可为具有挑战性的高性能设计带来最佳 PPA 结果
Cadence® Innovus™ Implementation System 针对最具挑战性的设计进行了优化，支持最新的 FinFET 16nm、14 nm、7nm和 5nm工艺，帮助您尽快开始设计，并迅速增加产能。Innovus 系统在组件摆放、优化、布线和时钟设置方面提供了一系列独特的新功能，其体系结构可应对设计流程中的上、下游步骤和影响。这种体系结构最大程度地减少了设计迭代，并可有效改善运行时长，助力产品快速上市。使用 Innovus 系统，您将可以构建风险更低的差异化集成系统。
Innovus 系统提供了多项关键功能。它采用了大规模并行架构，可以处理大型设计，并支持多核工作站上的多线程功能以及计算机网络上的分布式处理。
基于成熟的 NanoRoute ™ 引擎，新一代布线功能基于时序余量和功率，支持可感知布线轨道的时序优化，可尽早解决信号完整性问题并改善布线后的相关一致性。Innovus 系统包括全流程多目标技术，支持同时进行电气和物理优化。它还拥有通用的用户界面，以及附有综合和签核工具的用户命令，从而共享定制化流程。因此，您可以利用强大的报告和可视化功能，提高整个数字流程的设计效率和生产效率。
随着模块的单元数量和复杂性不断增加，需要在布局图中定位的宏的数量也呈爆炸式增长。Innovus 系统提供了混合宏和标准单元摆放功能，可以自动生成宏位置，从而将创建最佳平面图的时间从几天缩短到了几个小时。
机器学习计算机科学的最新进展与数字实现流程密切相关。Innovus 系统采用了机器学习技术，可为最具挑战性的高性能模块提供最佳 PPA 结果。设计人员可以对机器学习算法的训练进行全方位的控制，以确保算法可以满足其特定的设计要求。
Cadence’s Genus™ Synthesis Solution 与 Innovus 系统紧密集成，可实现从 RTL 综合(synthesis)到实现(implementation)的无缝过渡。借助 GigaPlace ™和GigaOpt ™ 引擎用与 Genus 物理综合的共享摆放和优化技术，该解决方案可为高级节点设计的收敛提供巨大优势。
由于最新的 FinFET 工艺节点中存在电压降，IR 和 EM 约束条件变得越来越重要。Innovus 系统包括全面的可感知电源完整性的组件摆放、优化、时钟树和布线功能，以确保在的实现过程中解决 IR 和 EM 违规问题，而不会影响最终的 PPA 结果。
Cadence 的 Tempus ™Timing Signoff Solution、 Quantus ™ Extraction Solution 以及 Voltus ™ IC Power Integrity Solution 与 Innovus 系统相互集成。通过这种集成，您可以在物理实现的早期阶段对寄生效应、时序、信号和电源完整性影响进行精确建模，并在这些电气指标上实现更快的收敛，从而更有效地完成设计收敛。
Resource Library
Video (10)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- 应用iSpatial流程达到卓越设计: 工欲善其事，必先利其器
- Pushing frequency, power and area with the iSpatial flow to achieve Design Excellence
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- Maximizing PPA on ARM’s Next-Generation High-Performance Processor Using the Latest Cadence Implementation and Signoff Tools/Flow
- Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership
- eInfochips Shortens Runtime on 300M Gate Count SoCs with Innovus Implementation System
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Press Releases (4)
- Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
- Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
- Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology
Demo Videos (5)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Customers
Our products enable the reception of broadband data and video content, requiring high levels of performance, small silicon die-size, and rapid time to market. Innovus Implementation System has provided us with unprecedented full-flow speed-up, so we can deliver reliable designs to market faster.
Dr. Paolo Miliozzi, Senior Director, SOC Technology and Physical Design, MaxLinear
We've tested the full Innovus Implementation System flow on some of our most congestion-challenged 28nm networking IP blocks and have achieved excellent results while seeing significant throughput improvements. The new Cadence solution has enabled us to resolve our most difficult timing requirements…
Fares Bagh, Vice President, Hardware and Architecture Engineering in Freescale's Digital Networking Group
Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.
Debashis Basu, SVP Engineering, Silicon and Systems Engineering, Juniper Networks
Innovus Implementation System provided us with substantial gains in quality of results and speed-up for our most challenging design.
Tatsuji Kagatani, Dept. Manager, Design Automation Dept., Elemental Technology Development Division at Renesas System Design Co., Ltd.
At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets. We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement…
Noel Hurley, General Manager, CPU Group, ARM
The Innovus Implementation System significantly improved the runtime on a critical multi-million-cell IP core compared to our previous solution. With runtimes improved to deliver more than a million cells per day of implementation throughput, we can confidently drive our aggressive schedules…
Robin Lu, Vice President of ASIC, Spreadtrum Communications
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