CadenceTECHTALK (Japan): 機能検証ソリューション・セミナー Verification Throughput and Smart Bug Hunting with the Cadence Verification Suite

このWebinarシリーズでは、広い設計対象に対応する検証への要求を満たし、設計品質向上と開発工期短縮の双方を達成する手法について解説いたします。

Webinar: Achieving Voltage Drop Requirements Using Integrated Optimization and Signoff

During this webinar we will discuss the latest techniques for IR drop optimization within the Innovus Implementation System, such as IR-aware placement, clock tree synthesis and power grid wire sizing, all based on the integrated Voltus voltage and power analysis and Tempus timing sign off engines. Attend this webinar to learn how to close IR drop constraints using an IR-aware implementation flow. Limited to Cadence customers with access to the digital implementation flow.

Webinar: Accelerate Design Productivity with Virtuoso ADE Explorer and Assembler

Join Cadence Training and Lead Application Engineer Bertram Winter and Application Engineer Ashika Ashok for our free, one-hour live webinar. Learn more about how to easily master Virtuoso ADE Explorer and Assembler and increase your design productivity at the same time.

CadenceTECHTALK (Japan): デジタルIC設計ソリューション・セミナー 2020 @HOME

高いレイアウト予見性と最高のPPAを実現する合成ツールのGenus™のご紹介、業界標準となりつつあるデジタル・インプリメンテーション・ツールのInnovus™の新機能紹介、また難易度の高い設計に必須となる統合されたサインオフソリューションをご紹介します。

Webinar: Chip-Level Thermal Analysis Using Celsius Thermal Solver

Transient thermal analysis is a critical factor in understanding thermal behavior, and the impact of dynamic thermal management on the performance of a chip, even more so for applications like automotive, data center, mobile, healthcare, and high-performance computing

Webinar (India): Leveraging In-Design DFM to Reduce Post-Layout Signoff Iterations

Join this free live webinar and learn how Cadence’s Allegro PCB DesignTrue DFM Technology offers industry’s first in-design DFM solution addressing manufacturing checks in real time as you design.

Webinar: Digital Implementation and Signoff – A Full Flow Overview

Bigger and more complex designs translate to more challenging PPA targets. To meet these challenges, the Cadence integrated digital full-flow offers innovations that work across individual tool boundaries through the integration of core engines and key technologies. Watch this webinar to learn how the Cadence digital full flow and its underlying products can help you beat your PPA goals ahead of schedule.

Webinar (Taiwan): Verify Clock Gates with the JasperGold SEC App

The Cadence JasperGold Sequential Equivalene Checking (SEC) App is the industry's most widely supported independent sequential equivalence checking product--providing a complete solution without the need for testbench development. Learn more about the app by joining Cadence for this free, one-hour live webinar.

Webinar Series: Front-End Power Analysis and Optimization

The majority of gains in low power occur in the early stages of design—in the architecture and microarchitecture levels. Being able to make effective decisions at those stages requires a combination of data and technology to accurately predict how they will translate into the final product, which traditionally has not been possible. Join us for this four-day webinar series to learn how to analyze and optimize designs to arrive at the lowest power end product.

CadenceTECHTALK (Japan): AWRオンライン・セミナー 2020 -July

AWR製品の技術的なご紹介、ケイデンスの各種製品と連携したソリューションについてご紹介します。