Webinar: Basics of CFD in 8 Weeks

Learn the basics of CFD in eight classes across eight weeks and gain hands-on experience using commercial, flow-simulation software! This is a free online course.

On-Demand CadenceTECHTALK: Cadence Cerebrus - How to Improve Your Chip Design Performance and Productivity Using Machine Learning (Korea)

In this webinar, we will highlight the critical technologies behind the new Cadence® Cerebrus™, Intelligent Chip Explorer and the RTL-to-signoff implementation flow to show how they can help you achieve up to 10X productivity 20% PPA improvements for implementation.

2021 Cadence中国技术巡回研讨会—深圳站

2021 CadenceCONNECT: China Technology Day is coming soon! This year, Cadence will hold its seminar in Shenzen, where we will bring you best practices and ideas. Come and join us!

Design Automation Conference 2021

Cadence is a proud Platinum sponsor of the 58th Design Automation Conference.

CadenceTECHTALK: MSA -システム解析フォーラム 2021

お客様の最先端の設計に新しいアイディアをもたらす、ケイデンスのMSA (Multiphysics System Analysis) 製品群。 これまでの解析セミナーから名称を改め、今回、新たに高周波設計環境のAWR製品も加え、装いも新たに「MSA-システム解析セミナー」として生まれ変わります。

CadenceCONNECT: Fostering a Photonics Ecosystem for Sustainable Adoption

Join Cadence for the sixth-annual CadenceCONNECT Photonics event on December 7-9 to find out what’s needed to foster the photonics ecosystem for sustainable adoption. Is it too hard to design? Too expensive? Not enough yield? What is missing?Foundry, industry, and academic experts will answer these questions and share proposals for how to bridge leftover gaps for reaching sustainable adoption.

CadenceTECHTALK: How to Improve Your Chip Design Performance and Productivity Using Machine Learning

Machine learning combined with distributed computing offers new capabilities to automate and scale RTL-to-GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects. During this webinar, we will explain key technologies behind the new Cadence® Cerebrus™ Intelligent Chip Explorer and the RTL-to-signoff implementation flow to show how they can help you achieve up to 10X productivity and 20% PPA improvements for implementation.

Bug Tracking with Indago Interactive for Specman

The Indago™ Debug Platform is optimized for scalability, supporting debug of simulation runs as well as emulation, where support for loading large source files and handling huge amounts of probe data is a must. Join this free Cadence Training Webinar to learn how to improve your Specman debug experience using the Indago Debug Platform.

CadenceCONNECT: Club Formal Europe 2021

Ready to learn and share ideas about the latest formal verification best practices? Don´t miss this chance to extend your verification expertise and broaden your learning about the latest advances in the field. With the opportunity to hear from members of the Cadence® Jasper™ R&D team about the technology, roadmap, and use cases, be sure to attend this digital event. Including deep-dive sessions, technical forum for intermediate and advanced users of Jasper technology. As with the in-person events of past years, expert-to-expert interaction will be enabled through the Zoom platform in the Q&A session after the presentations.

CadenceTECHTALK: Tempus Aging Aware STAで経年劣化の対策とPPAの更なる向上を！！

車載、医療、工業などをはじめ、重要な半導体製品は長期にわたって絶対的に安全・安定な動作が求められます。現在、安定な動作と寿命を延ばす目的で、設計現場では経年劣化を考慮した過剰なマージン設定が行われています。これはエリアの増大や消費電力の増加、デザイン収束までの時間の長大化の一因となっています。 Liberate™とTempus™を組み合わせたこのソリューションはこの問題を解決できる画期的なアプローチです。