Resource Library
Video (9)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- Pushing frequency, power and area with the iSpatial flow to achieve Design Excellence
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership
- Maximizing PPA on ARM’s Next-Generation High-Performance Processor Using the Latest Cadence Implementation and Signoff Tools/Flow
- eInfochips Shortens Runtime on 300M Gate Count SoCs with Innovus Implementation System
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Demo Videos (5)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Press Releases (5)
- ケイデンス、革新的なマシンラーニングベースの設計システム新製品Cerebrusを発表、デジタル設計のリーダーシップを拡大、クラス最高の生産性と結果品質を実現 | Cadence
- ケイデンスのデジタル設計およびカスタム/アナログ設計EDAフローが TSMCのN6およびN5プロセステクノロジで認証を取得 | Cadence
- ケイデンスのデジタル設計フルフロー、マシンラーニングを活用し、 QoR改善、設計スループット最大3倍高速化の実現に向け最適化 | Cadence
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process | Cadence
- Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology | Cadence
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