Overview
Industry’s Fastest, Most Accurate Parasitic Tool with Up to 5X Accelerated Extraction
The Cadence Quantus Extraction Solution is the industry’s most trusted signoff parasitic extraction tool, leading in advanced-node design adoptions and on-time tapeout deliveries. This single, unified tool supports both cell-level and transistor-level extractions during design implementation and signoff. It is foundry certified down to 2nm and is an essential component of our in-design methodology, working seamlessly with the Innovus Implementation System and Virtuoso platform.
The Quantus Extraction Solution serves as a linchpin for designers to maximize their use of Rs and Cs on both digital-level and transistor-level flows, ensuring on-time tapeout deliveries. Customers depend on Quantus’ advanced analysis features within Quantus DSPF Interactive Output (Quantus I-DSPF Output), Smart View, Extracted View, and DSPF to boost productivity and expedite design closure.
Key Benefits
Advantages of Parasitic Extraction Innovation in Quantus to Deliver Superior PPA
Faster Design Closure
Fastest single-corner and multi-corner runtimes
Enhanced Accuracy
Intelligent parasitic extraction providing the most accurate RCs for both digital and custom/analog designs
Improved Productivity
Faster convergence with tight integration with Innovus Implementation System and Virtuoso Studio
Ease of Use
Intuitive user interface with enhanced interactive debugging and visual insights allows effortless navigation for custom/analog designs in Virtuoso Studio
Features
Achieve Full Optimization and Signoff of Your Design Through Machine Learning (Neural Network) Technology
Offerings
Quantus Extraction Solution
Quantus Insight Solution
- Proactively detects and resolves critical parasitic elements contributing to design challenges in the early design phase
- Empowers designers with comprehensive analyses, such as detailed what-if scenarios, resistance analysis, and layer-wise analysis, plus more, to drive design efficiency
- Offers intuitive visualization features that transform complex data into clear, digestible design insights
- A seamless integration with the Cadence Virtuoso environment, namely Virtuoso Studio with iQuantus Insight Solution that optimizes design debugging workflows
Quantus DSPF Interactive Output
- Offers enhanced interactive debugging enabling more efficient navigation of parasitic data
- Real-time feedback on the impact of design changes accelerating design debugging cycles
- Visual aids that represent parasitic elements and their impact on the circuit
- User-friendly interface enabling effortless navigation through design data to avoid manually sifting through extensive ASCII files
- Provides a revolutionized debugging process delivering the fastest design closure, improved productivity, and faster turnaround time
Quantus Field Solver
- Cloud-ready and massively parallel including the smallest netlist and lowest memory consumption
- Foundry certified and qualified down to 2nm
- Best-in-class accuracy compared to other methodologies
- Seamless integration with Innovus Implementation System, Virtuoso platform, Voltus-XFi Custom Power Integrity Solution, Tempus Timing Solution, and Spectre Circuit Simulation
Customer Stories
See What Customers Have to Say About
Quantus Extraction Solution
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.
Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear
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