RF Spurs Impacting Your Performance? Not Anymore!
Quantus' Substrate Noise Analysis Functionality
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Key Benefits
- Leader in 3nm customer adoptions for both digital and custom/analog designs
- Trusted by all leading customers and foundries—provides best-in-class accuracy for all design nodes for faster design convergence
- 5G ready with market-leading functionality to support all 5G/RF designs
- Massively parallel and cloud-ready for fastest single and multi-corner performance with linear scaling to 1000s of CPUs for on-time tapeout
- Built-in massively parallel and cloud-ready 3D Field Solver, Quantus FS, for all critical and advanced-node designs for accurate parasitics
- Provides many market-leading analysis features and functionality to support both digital and transistor designs extraction
- Foundry certified at TSMC down to 3nm
- Certified for advanced-node processes at other leading foundries worldwide
The Cadence® Quantus™ Extraction Solution is the industry’s most trusted signoff parasitic extraction tool, and is a leader in 3nm design adoptions and tapeouts. As a single, unified tool, the Quantus solution supports both cell-level and transistor-level extractions during design implementation and signoff. It’s an integral component of our in-design methodology with both the Innovus™ Implementation System and Virtuoso® platforms.
The Quantus Extraction Solution is the linchpin that allows designers to do more with Rs and Cs on both digital- and transistor-level flows, assuring on-time tapeout.
The Quantus solution is central to full flow for both digital and transistor extraction
Related Products
Customers
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.
Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear
Training
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview
