Digital Design and Signoff Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
Implementation
- Conformal ECO
- Innovus Block Implementation with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Hierarchical Implementation with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Innovus Low-Power Flow with Stylus Common UI
- Low-Power Flow with Innovus Implementation System (Libraries not included)
- Virtuoso Digital Implementation
- Want fewer tapeout bugs? Run Conformal Equivalence Checks!
Silicon Signoff
- Basic Static Timing Analysis
- Tempus Signoff Timing Analysis and Closure
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
Synthesis and Test
- Advanced Synthesis with Genus Stylus Common UI
- Advanced Synthesis with Genus Synthesis Solution
- Cadence RTL-to-GDSII Flow
- Design for Test Fundamentals
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Genus Synthesis Solution with Stylus Common UI
- Joules™ Power Calculator
- Low-Power Synthesis Flow with Genus Stylus Common UI (Libraries not included)
- Low-Power Synthesis Flow with Genus Synthesis Solution (Libraries not included)
- Modus DFT Software Solution
- Test Synthesis Using Genus Synthesis Solution
- Test Synthesis with Genus Stylus Common UI
- Want fewer tapeout bugs? Run Conformal Equivalence Checks!