Digital Design and Signoff Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
Implementation
- Advanced Synthesis with Genus Stylus Common UI
- Artificial Intelligence and Machine Learning Fundamentals
- Cadence Cerebrus Intelligent Chip Explorer
- Innovus Block Implementation with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Hierarchical Implementation with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Innovus Low-Power Flow with Stylus Common UI
- Low-Power Flow with Innovus Implementation System
- Virtuoso Digital Implementation
Silicon Signoff
- Basic Static Timing Analysis
- Certus Signoff Closure Solution with Stylus Common UI
- Tempus Signoff Timing Analysis and Closure
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Voltus InsightAI
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
Synthesis and Test
- ATPG Flow with Modus DFT Software Solution
- Advanced Synthesis with Genus Stylus Common UI
- Design for Test Fundamentals
- Diagnostics With Modus DFT Software Solution
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Low-Power Synthesis Flow with IEEE 1801
- Genus Physical Synthesis Flow
- Genus Synthesis Solution with Stylus Common UI
- Joules Power Calculator
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Test Synthesis with Genus Stylus Common UI