Xcelium Logic Simulation

Cadence^® Xcelium™ Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC^®, e, UVM, mixed signal, low power, and X-propagation. It leverages single-core and multi-core simulation technology for best individual test performance and machine learning-optimized regression technology for best regression throughput.

Xcelium single-core simulation delivers best-in-class compile, performance, and throughput with compute platform flexibility, providing:

• Continuous performance optimizations for new design styles and latest coding practices
• Up to 10X compile speedup with Xcelium incremental and parallel builds
• Throughput efficiency using save/restore with dynamic test reload
• Platform support for x86, Arm^®, and cloud compute platforms

Xcelium multi-core simulation is for the long-pole tests in your regression. Xcelium simulation integrates multi-core technology to reduce throughput latency, providing:

• Up to 2X performance boost for RTL-directed tests
• Up to 10X performance boost for gate-level ATPG and BIST tests, both zero delay and SDF annotated

Xcelium Logic Simulation with machine learning technology (Xcelium ML) provides machine learning-optimized regression. It makes randomized regressions faster by instructing the Xcelium simulation kernel and offers:

• Up to 5X regression efficiency with similar coverage
• User-directed regression goals, such as maximum throughput, stress design instances, and replacing directed tests with randomized tests

Advanced Features

Safety

Xcelium Safety is an integral part of the Cadence Safety Solution targeting safety-critical applications for faster ISO 26262 certification. It provides high performance native engines for serial and concurrent fault injection and simulation. The native twin engines are complementary: the concurrent engine provides best-in-class throughput and is very useful in running the entire fault campaign, while the serial engine is useful in flow setup and fault debug. Both engines use identical flow, and users can easily switch back and forth. The native integration of the fault simulation engines enables unified compile, re-use of UVM testbench, and flows for both functional and safety verification, enhancing performance, productivity, and throughput, significantly. As part of the Cadence Safety Platform, it is integrated with the Midas Safety Platform for FMEDA-based functional safety verification. Fault campaign management (FCM) can be applied for optimized coverage-based test selection, smart run algorithms to reduce fault simulation time, and fault pruning using the JasperGold FSV App. The fault result database is also unified for merging diagnostic coverage across different engines as well as hierarchical merge from IP to SoC level.

Low-Power

Cadence has been at the forefront on low-power technology, introducing CPF in 2005 and also supporting UPF introduced in 2006 and transitioned to IEEE 1801 in 2009. Xcelium simulation supports both CPF and UPF/IEEE 1801 for low-power simulation.

Mixed-Signal

The Xcelium simulator with mixed-signal option covers advanced digital features such as UVM, SystemVerilog Testbench, UPF/CPF, and SystemC. It also supports the simulation of languages such as Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog Real Number Modeling (SVRNM), SystemVerilog, and mixed-signal features along with SPICE, and other digital-centric mixed-signal technologies, such as low power and mixed signal, code coverage and mixed signal, functional safety and mixed signal, and incremental elaboration and mixed signal.

Constrained Random

Cadence simulators have been the leaders of constrained random technology and methodology, starting with Specman^® Simulation and later being the key driver behind UVM methodology and library standardization. Xcelium constraint solvers are the latest generation of the technology and include a powerful new constraint analyzer and constraint-solving performance-profiling tool.

X-Propagation

X-propagation is a feature that avoids X-optimism in LRM-compliant RTL simulation. This allows for early detection of X issues and avoids surprises later in gate-level simulations. Xcelium simulation supports two modes for X-propagation. There is the more pessimistic Forward-Only-X (FOX) mode and less pessimistic Compute-As-Ternary (CAT) mode.