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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
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Xcelium Logic Simulation

Industry-leading simulation for best verification throughput

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Key Benefits

  • Compile/build performance
    • Automated parallel and incremental build
  • Regression throughput
    • Throughput from some single-core performance (including gate-level, RTL, and SV testbench)
    • Throughput and productivity improvement with save/restore
    • Faster regressions with machine learning
  • Reduced latency
    • Multi-core performance for long-pole tests
  • Native support for advanced use cases
    • X-propagation, low-power (UPF/CPF), mixed-signal, and constrained random
  • Support for multiple compute platforms
    • Supported on x86 and Arm servers
    • Supported on the cloud

Cadence® Xcelium™ Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed signal, low power, and X-propagation. It leverages single-core and multi-core simulation technology for best individual test performance and machine learning-optimized regression technology for best regression throughput.

Xcelium single-core simulation delivers best-in-class compile, performance, and throughput with compute platform flexibility, providing:

  • Continuous performance optimizations for new design styles and latest coding practices
  • Up to 10X compile speedup with Xcelium incremental and parallel builds
  • Throughput efficiency using save/restore with dynamic test reload
  • Platform support for x86, Arm®, and cloud compute platforms

Xcelium multi-core simulation is for the long-pole tests in your regression. Xcelium simulation integrates multi-core technology to reduce throughput latency, providing:

  • Up to 2X performance boost for RTL-directed tests
  • Up to 10X performance boost for gate-level ATPG and BIST tests, both zero delay and SDF annotated

Xcelium Logic Simulation with machine learning technology (Xcelium ML) provides machine learning-optimized regression. It makes randomized regressions faster by instructing the Xcelium simulation kernel and offers:

  • Up to 5X regression efficiency with similar coverage
  • User-directed regression goals, such as maximum throughput, stress design instances, and replacing directed tests with randomized tests

Advanced Features

Low-Power

Cadence has been at the forefront on low-power technology, introducing CPF in 2005 and also supporting UPF introduced in 2006 and transitioned to IEEE 1801 in 2009. Xcelium simulation supports both CPF and UPF/IEEE 1801 for low-power simulation.

Mixed-Signal

The Xcelium simulator with mixed-signal option covers advanced digital features such as UVM, SystemVerilog Testbench, UPF/CPF, and SystemC. It also supports the simulation of languages such as Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog Real Number Modeling (SVRNM), SystemVerilog, and mixed-signal features along with SPICE, and other digital-centric mixed-signal technologies, such as low power and mixed signal, code coverage and mixed signal, functional safety and mixed signal, and incremental elaboration and mixed signal.

Constrained Random

Cadence simulators have been the leaders of constrained random technology and methodology, starting with Specman® Simulation and later being the key driver behind UVM methodology and library standardization. Xcelium constraint solvers are the latest generation of the technology and include a powerful new constraint analyzer and constraint-solving performance-profiling tool.

X-Propagation

X-propagation is a feature that avoids X-optimism in LRM-compliant RTL simulation. This allows for early detection of X issues and avoids surprises later in gate-level simulations. Xcelium simulation supports two modes for X-propagation. There is the more pessimistic Forward-Only-X (FOX) mode and less pessimistic Compute-As-Ternary (CAT) mode.

Contact Us

TRAINING COURSES

Cadence Delivers Verification Throughput

Cadence Delivers Industry-Leading Logic Simulation

Cadence Introduces Xcelium ML

Maximizing Xcelium Simulation Performance

  • Related Products

    • Cadence Verification Suite
    • Perspec System Verifier
    • Cadence Specman Elite
    • vManager Verification Management
    • Verification IP
    • JasperGold Formal Verification Platform
    • Palladium Emulation
    • Spectre Circuit Simulator
    • Spectre AMS Designer
Resource Library

Video (21)

  • Accelerate DFT Simulations with Xcelium Multi-Core Technology
  • Up to 5x More Efficient Regressions with Xcelium
  • Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
  • Verification Enhances Confidence in Defense Program Success
  • Xcelium Performance Improvement Methodologies
  • Solutions for MATLAB modeling verification within Cadence simulator
  • Process based Save Restart and Dynamic Test Flows
  • Xcelium Parallel Simulator on Cavium Arm-based ThunderX2
  • Cadence Delivers Verification Throughput
  • Xcelium for Fast Simulation and Throughput
  • Cadence Delivers Industry-Leading Logic Simulation
  • Cadence Introduces Xcelium ML
  • Cadence Introduces Xcelium ML
  • Get up to 5x increase in verification regression throughput with Cadence Xcelium-ML
  • Accelerate Your Time to Debug Root Cause
  • Quick Coverage Closer with JasperGold UNR App. A Deep-Dive Session.
  • Maximizing Xcelium Simulation Performance - India
  • New Key Features of Xcelium for Advanced Mixed-Signal Verification
  • The Benefits of Running the Xcelium Parallel Logic Simulator on Cavium’s Arm Based ThunderX2

Webinar (6)

  • Accelerate DFT Simulations with Xcelium Multi-Core Technology
  • Accelerate Your Time to Debug Root Cause
  • Quick Coverage Closer with JasperGold UNR App. A Deep-Dive Session.
  • Maximizing Xcelium Simulation Performance - India

Customer Presentation (3)

  • Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
  • Verification Enhances Confidence in Defense Program Success
  • Solutions for MATLAB modeling verification within Cadence simulator

Demo (1)

  • Xcelium Parallel Simulator on Cavium Arm-based ThunderX2

Press Releases (10)

  • Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation with up to 5X Faster Regressions
  • Cadence Optimizes Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development
  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
  • Cadence Verification Suite Enabled on Arm-Based HPC Datacenters
  • Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design
  • Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator
  • Cadence Launches Protium S1 FPGA-Based Prototyping Platform for Early Software Development
  • Cadence Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator

Presentation (4)

  • Up to 5x More Efficient Regressions with Xcelium
  • Xcelium Performance Improvement Methodologies
  • Process based Save Restart and Dynamic Test Flows
  • Speed Up Your Mixed-Signal Verification with Spectre X Simulator

Technical Brief (2)

  • Finding Hidden Randomization Tricks with Machine Learning
  • Innovative HPC and Verification Technology Speed SoC Development Technical Brief
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre Silicon Hardware Debug and Software Validation 04/05/2021

  • Cadence Brings Verification IP to the Chip Level with New System VIP Solution 10/13/2020

  • Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform 08/18/2020

  • Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation with up to 5X Faster Regressions 08/12/2020

  • Cadence Optimizes Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development 05/26/2020

Blogs VIEW ALL
Customers

Kioxia has utilized Xcelium simulation for a variety of our designs. With the new Xcelium ML, we’ve seen a 4X shorter turnaround time in our fully random regression runs to reach 99% function coverage of original, and plan to use this technology in production designs to shorten the time to market for Kioxia’s business.

Kazunari Horikawa, senior manager, Design Technology Innovation Division at Kioxia Corporation

Read More or View All Customers

The Xcelium Simulator has demonstrated a 4X speed-up for gate-level simulation and 5X for RTL simulation on ARM®-based SoC designs. Based on these results, we expect Xcelium can enhance our ability to deliver the most complex SoCs in a fast and highly reliable way.

Hobson Bullman, general manager, Technology Services Group, ARM

Read More or View All Customers

Fast, scalable simulation is key for us to meet the tight development schedules of our complex 28nm FD-SOI SoCs and ASICs for smart driving and industrial IoT. We measured 8X faster serial-mode DFT performance with the Cadence Xcelium Simulator, and selected it as the standard simulation solution...

Francois Oswald, CPU team manager, STMicroelectronics

Read More or View All Customers

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