Introduction to Genus Synthesis iSpatial Flow
Uniﬁed physical optimization for better predictability and PPA
The ultimate goal of the Cadence® Genus™ Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design and the highest quality of results (QoR) in final implementation.
The Genus synthesis solution provides up to 5X faster synthesis turnaround times and scales linearly beyond 10M instances. In addition, a new physically aware context-generation capability reduces iterations between unit- and chip-level synthesis by 2X or more. From this powerful combination, you can gain an up to 10X improvement in RTL design productivity. What’s more, a new global, analytical, architecture-level optimization engine can reduce datapath area by up to 20% without any impact on performance.
A new common user interface that the Genus synthesis solution shares with Cadence Innovus™ Implementation System and Cadence Tempus™ Timing Signoff Solution streamlines flow development and simplifies usability across the complete Cadence digital flow. The new user interface includes unified database access, MMMC timing configuration and reporting, and low-power design initialization.
Processors for automotive and industrial markets are driving higher levels of integration and complexity. This requires larger design partitions to deliver the efficiencies and time to market demanded by our customers.
Anthony Hill, Director of Processor Technology, Texas Instruments
At Imagination, we regard the ability to perform rapid synthesis as a key enabler for our customers to better explore the design space and achieve the best PPA within ever-shrinking tapeout schedules.
Tony King-Smith, Executive Vice President of Marketing, Imagination
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview