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  • Products

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      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

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      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

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Genus Synthesis Solution

Delivering the best possible productivity during RTL design and the highest quality of results (QoR) in final implementation

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Key Benefits

  • Up to 10X better RTL design productivity
  • Up to 5X faster turnaround times, with linear scalability beyond 10M instances
  • At least 2X reduction in iterations between unit-, block-, and chip-level synthesis
  • Timing and wirelength within 5% of place and route in the Cadence Innovus Implementation System
  • Up to 20% reduction in datapath area without any impact on performance
  • Part of the Cadence Safety Solution providing automated safety mechanism insertion and optimization

 

The ultimate goal of the Cadence® Genus™ Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design and the highest quality of results (QoR) in final implementation.

The Genus synthesis solution provides up to 5X faster synthesis turnaround times and scales linearly beyond 10M instances. In addition, a new physically aware context-generation capability reduces iterations between unit- and chip-level synthesis by 2X or more. From this powerful combination, you can gain an up to 10X improvement in RTL design productivity. What’s more, a new global, analytical, architecture-level optimization engine can reduce datapath area by up to 20% without any impact on performance.

A new common user interface that the Genus synthesis solution shares with Cadence Innovus™ Implementation System and Cadence Tempus™ Timing Signoff Solution streamlines flow development and simplifies usability across the complete Cadence digital flow. The new user interface includes unified database access, MMMC timing configuration and reporting, and low-power design initialization.

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Introduction to Genus Synthesis iSpatial Flow

Unified physical optimization for better predictability and PPA
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Pushing frequency, power and area with the iSpatial flow to achieve Design Excellence

RTL Design, Genus Style: The scoop on how you can get hours of your life back

  • Related Products
    • Cadence Joules RTL Design Studio
    • Innovus Implementation System
    • Stratus High-Level Synthesis
    • Joules RTL Power Solution
    • Virtuoso Digital Implementation
Videos

New Synthesis Tool Improves RTL Productivity and Quality of Results

Massive Parallelism in Action: See how multiple levels of parallelism accelerate RTL synthesis.

Boost RTL Productivity with 2X Fewer Unit-Level Iterations

In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated

New Synthesis Tool Optimizes Datapath for Better PPA

New RTL Synthesis Tool Saves Hours of Your Time

News ReleasesVIEW ALL
  • Cadence Advances Design and Engineering for Europe’s Manufacturers on NVIDIA Industrial AI Cloud 06/11/2025

  • Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications 06/12/2024

  • Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design 04/24/2024

  • Phison Deploys Cadence Cerebrus AI-Driven Chip Optimization to Accelerate Product Development 01/22/2024

  • GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform 01/10/2024

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Customers

Processors for automotive and industrial markets are driving higher levels of integration and complexity. This requires larger design partitions to deliver the efficiencies and time to market demanded by our customers.

Anthony Hill, Director of Processor Technology, Texas Instruments

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At Imagination, we regard the ability to perform rapid synthesis as a key enabler for our customers to better explore the design space and achieve the best PPA within ever-shrinking tapeout schedules.

Tony King-Smith, Executive Vice President of Marketing, Imagination

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