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DESIGN EXCELLENCE

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CADENCE CLOUD

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

  • Logic Equivalence Checking
  • Innovus Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
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  • Achieve best PPA with the next-generation Digital Full Flow solution Learn More
  • Address digital implementation challenges with machine learning Watch Now

Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions
  • Flows
  • Solve analog simulation challenges in complex designs Watch Now
  • See how the Virtuoso Design Platform addresses advanced custom IC and system design challenges Watch Now

System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

  • Debug Analysis
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  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP
  • Flows
  • Prototype your embedded software development Watch Now
  • Learn how early firmware development enabled first silicon success at Toshiba Memory Watch Now

IP

An open IP platform for you to customize your app-driven SoC design.

  • Interface IP
  • Denali Memory IP
  • Tensilica Processor IP
  • Analog IP
  • System / Peripherals IP
  • Verification IP
  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
  • Meeting the needs of 5G communication with Tensilica® ConnX B20 DSP IP Download Now

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
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  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Thermal Solutions
  • System Analysis Resources Hub

Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • What's New in Allegro
  • What's New in Sigrity
  • RF / Microwave Design
  • Flows
  • Advanced PCB Design & Analysis Blog
  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
  • Augmented Reality Lab Tools

AI / Machine Learning

AI IP Portfolio

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See how our customers create innovative products with Cadence Explore Now

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TRAINING

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Learn how Intelligent System Design™ powers future technologies Learn More
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View all Products
  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • SUPPORT
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
  • COMPANY
      • CORPORATE
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      • CORPORATE
        • About Us
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      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
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        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
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        • Alliances
        • Corporate Social Responsibility
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      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers

Products

Integrated design and verification technologies and methodologies for chips to packages to boards to systems

  • Overview
  • Videos
  • News and Blogs
  • Customers
  • Products A-Z
  • Products

    • Cadence Verification Suite
    • Digital Design and Signoff
    • Custom IC / Analog / RF Design
    • IC Package Design and Analysis
    • PCB Design and Analysis

Having the right tools to design and verify your chips has never been more important. After all, you're trying to stay on top of Moore's Law and meet the design challenges that come with this. However, with electronic circuits being an integral component of so many products, design and verification also extends to packages, boards, and the whole system.

To help you create high-quality, differentiated electronic products, Cadence offers a broad portfolio of tools to address an array of challenges related to custom IC, digital, IC package, and PCB design and system-level verification. Find the tools and methodologies you need to meet your power, performance, and area targets; overcome mixed-signal design constraints; achieve faster design closure; and much more.

Videos

NVIDIA Handles Complexity with Palladium Z1 Platform

The New Sound of Analog Design: Simplify Design Verification with Virtuoso ADE Product Suite

RTL Design, Genus Style: The scoop on how you can get hours of your life back

In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.

Celebrating 25 Years of Virtuoso Innovation

News ReleasesVIEW ALL
  • Cadence to Acquire NUMECA to Expand System Analysis Capabilities with Computational Fluid Dynamics 01/20/2021

  • Cadence Announces Fourth Quarter and Fiscal Year 2020 Financial Results Webcast 01/08/2021

  • Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5/3D Chip Designs 12/16/2020

  • Samsung Foundry Adopts Spectre X Simulator for 5nm Design 12/08/2020

  • Rockley Photonics Collaborates with Cadence to Create a High-Performance System for Hyperscale Data Centers 12/02/2020

Blogs VIEW ALL
Customers

Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.

Debashis Basu, ‎SVP Engineering, Silicon and Systems Engineering, Juniper Networks

Read More or View All Customers

The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.

Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei

Read More or View All Customers

Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.

Martin Kejhar, Senior Technical Staff Engineer and Scientist, ON Semiconductor

Read More or View All Customers

Products A-Z

A

  • Allegro Design Authoring
  • Allegro Design Entry Capture/Capture CIS
  • Allegro Design Publisher
  • Allegro ECAD-MCAD Library Creator
  • Allegro EDM Solution
  • Allegro FPGA System Planner
  • Allegro Package Designer Plus
  • Allegro Package Designer Plus Silicon Layout Option
  • Allegro Package Designer Plus SiP Layout Option
  • Allegro PCB Designer
  • Allegro PCB Librarian
  • Allegro PCB Symphony Team Design Option
  • Allegro PCB Symphony Team Design Option for IC Packaging
  • Allegro PSpice System Designer
  • Allegro Pulse
  • AWR Analyst Software
  • AWR AXIEM Analysis
  • AWR Design Environment Platform
  • AWR Microwave Office
  • AWR Software Options
  • AWR VSS Software

C

  • Celsius Thermal Solver
  • Clarity 3D Solver
  • Clarity 3D Transient Solver

E

  • EMX Planar 3D Solver

G

  • Green Hills and Cadence Solutions

I

  • Indago Embedded Software Debug

J

  • JasperGold Control and Status Register App
  • JasperGold Coverage Unreachability App
  • JasperGold Design Coverage Verification App
  • JasperGold Formal Verification Platform
  • JasperGold FPV App
  • JasperGold FSV App
  • JasperGold Security Path Verification App
  • JasperGold Sequential Equivalence Checking App

L

  • Legato Memory Solution
  • Legato Reliability Solution
  • Liberate AMS Mixed-Signal Characterization
  • Liberate Characterization Solution
  • Liberate LV Library Validation Solution
  • Liberate MX Memory Characterization
  • Liberate Trio Characterization Suite
  • Liberate Variety Statistical Characterization

M

  • MathWorks and Cadence Solutions

O

  • OrbitIO Interconnect Designer

P

  • Passives
  • Perspec System Verifier

S

  • Sigrity Advanced PI
  • Sigrity Advanced SI
  • Sigrity Aurora
  • Sigrity Broadband SPICE
  • Sigrity Extraction
  • Sigrity IBIS Modeling
  • Sigrity OptimizePI
  • Sigrity PowerDC
  • Sigrity PowerSI
  • Sigrity SPEED2000
  • Sigrity SystemSI
  • Sigrity Topology Explorer
  • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
  • Sigrity XcitePI Extraction
  • Sigrity XtractIM
  • SiP Digital Architect
  • Spectre Accelerated Parallel Simulator
  • Spectre AMS Designer
  • Spectre eXtensive Partitioning Simulator (XPS)
  • Spectre RF Option
  • Spectre Simulation Platform
  • Spectre X Simulator

V

  • Verification IP (VIP) Catalog
  • Virtual System Platform
  • Virtuoso ADE Assembler
  • Virtuoso ADE Explorer
  • Virtuoso ADE Product Suite
  • Virtuoso ADE Verifier
  • Virtuoso Analog Design Environment
  • Virtuoso DFM
  • Virtuoso Integrated Physical Verification System
  • Virtuoso Layout Suite
  • Virtuoso Layout Suite EAD
  • Virtuoso RF Solution
  • Virtuoso Schematic Editor
  • Virtuoso Space-Based Router
  • Virtuoso System Design Platform

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