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  • Products

    • Products

      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

      System Design & Analysis

      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

    • All Analog IC Design Products
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    • Artificial Intelligence

    • 3D-IC Design

    • Advanced Node

    • Arm-Based Solutions

    • Cloud Solutions

    • Computational Fluid Dynamics

    • Functional Safety

    • Low Power

    • Mixed-signal

    • Molecular Simulation

    • Multiphysics System Analysis

    • Photonics

    • RF / Microwave

    Designed with Cadence See how our customers create innovative products with Cadence
    Explore Cadence Cloud Now Explore Cadence Cloud Now
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System Design and Verification

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System Design and Verification Learning Map

Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.

Academic Curricula
  • Digital Design and Verification Academic Curriculum
Digital IC Design Fundamentals
  • Digital IC Design Fundamentals
Emulation and Acceleration
  • Protium Introduction
Formal Verification
  • Jasper App For Early Design Verification
  • Jasper Design Bringup Training
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  • Palladium Introduction
  • Perspec System Verifier - Basic
  • SystemVerilog Assertions
Midas
  • MIDAS Safety Analysis Authoring
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Onboarding Curricula
  • System Design and Verification, Digital Physical Design and Signoff Onboarding
Planning and Management
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Scripting
  • Introduction to Tk
  • Perl for EDA Engineering
  • Tcl Scripting for EDA
  • Tcl Scripting for EDA + Intro to Tk
Simulation and Testbench and Debug
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  • Perspec System Verifier - Basic
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  • Xcelium Fault Simulator
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Specman and UVMe
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SystemC
  • C++ Language Fundamentals
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  • SystemC Synthesis with Stratus HLS
  • SystemC Transaction-Level Modeling (TLM 2.0)
SystemVerilog and UVM
  • Essential SystemVerilog for UVM
  • SystemVerilog Accelerated Verification with UVM
  • SystemVerilog Advanced Register Verification Using UVM
  • SystemVerilog for Design and Verification
Tech Domain Certification Programs
  • Front End Digital Design and Verification Language and Methodology Domain Certification
  • Simulation, Coverage, Debug, and Verification Planning & Management Domain Certification
  • System Verilog Assertions (SVA) and Formal Verification Domain Certification
Verification IP
  • UCIe VIP Introduction
  • VIP Basic Building Blocks and Usage
Verilog and VHDL
  • VHDL Language and Application
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