Innovus Implementation System

The Innovus Implementation System features the new GigaPlace engine, which changes the way placement is done and enhances PPA. Placement has traditionally been “timing-aware” and “lightly” integrated with other engines in the implementation system, such as timing analysis and optimization. The GigaPlace engine, on the other hand, is slack driven and tightly integrated. With this approach, the engine helps place the cells in a timing-driven mode by building up the slack profile of the paths and performing the placement adjustments based on these timing slacks.

The GigaPlace engine models accurate electrical constraints and physical constraints, such as floorplan, route topology-based wire length, and congestion. It also integrates the mathematical model of Cadence’s timing- and power-driven optimization engine, another component of the Innovus Implementation System. This integration makes concurrent, convergent optimization of electrical and physical metrics possible. You are also equipped to extract your design intent automatically from the electrical constraints, so you can achieve better optimization for physical metrics.

The Innovus Implementation System features a global optimization strategy and a novel numerical solver to avoid the trap of local minima. This avoids costly design iterations between different steps of the flow and results in a faster design closure with the best PPA.

In addition to solving for overlap and wire length, the GigaPlace engine solves for slack that is driven by gate delay, false/ multi-cycle paths, layer assignment, and congestion timing effects. As a result, you get better total negative slack (TNS)/ worst negative slack (WNS), wire length, congestion, spreading, and power. In summary, the GigaPlace engine is:

Pin access has become a new design closure metric. The GigaPlace engine, as shown in Figure 1, accounts for pin density, providing an adaptive pin access flow that automatically spaces cells based on the neighboring instance’s pin-access restrictions, and not just high local pin density. A proprietary algorithm in the tool globally plans how the router will access each pin (this is based on instances, not library cells). The GigaPlace engine has a cell spreading cost function that considers more design rule check (DRC) rules and pre-routes. An optimization cost function considers both horizontal and vertical cell spreading, and there’s an in-row space juggling function during legalization.

The GigaPlace engine, with its automatic density screen technology, simplifies the process of resolving congestion by automatically adding density screens in floorplan induced high traffic areas. The algorithm analyzes floorplans, traffic patterns, and congestion maps to keep standard cells away from the congested area, such as narrow channels, notches, and macro boundaries. This helps reduce congestion without requiring you to add these density screens yourself.

The Innovus Implementation System features a next-generation clock concurrent optimization engine with true multithreading, enhanced useful skew, and flow integration. The engine merges physical optimization with clock-tree synthesis (CTS), simultaneously building clocks and optimizing logic delays based directly on a propagated clocks model. All the optimization decisions are based on true propagated clocks and account for clock gates, inter-clock paths, and on-chip variation (OCV) derates.

A new FlexH feature in the implementation system provides a structure that is topologically as close to an H-tree as possible, with tradeoffs between different soft and hard constraints. This feature democratizes the H-tree approach to a real-world SoC design environment. Without this capability, designers would typically use mesh or a hand-created tree—architecturally limited and power-hungry approaches. The FlexH feature employs an advanced heuristic search algorithm, which explores millions of different possible tree structures to find the best compromise between avoiding blockages and power rails. The algorithm adheres to partition, module, and powerdomain constraints and optimizes insertion delay, power, and skew.

The Innovus Implementation System accelerates digital design TAT through various features, including its full-flow massively parallel architecture. The architecture, which supports multi-threaded tasks simultaneously on multiple CPUs, is designed such that the system can produce best-in-class TAT with standard hardware, which is normally 8-16 CPUs per box. In addition, for designs with a larger instance count, the flow can scale over a larger number of CPUs. The system’s advanced timing- and power- driven optimization engine provides threaded MMMC timing. As the number of MMMC views increases, the engine delivers a sub-linear speedup.

The system’s routing engine is designed such that routing and post-route closure are handled on additional CPUs—more than 100 if needed for larger designs. Backed by its processing speed, the routing engine simultaneously evaluates and optimizes interconnect topology based on the effects on timing, area, power, manufacturability, and yield. With its correct-by-construction approach, the engine can resolve potential double patterning conflicts on the fly to create a routing topology that is correct for double patterning and DRC the first time and also more area efficient. The engine is equipped with a deterministic multithreaded backplane, provides full-flow timing correlations, and offers a flexible 2D/3D congestion mode. It also features a track-based optimization algorithm, which fixes signal integrity issues before detail routing, reduces the timing jump between pre-route and post-route, and enables faster design closure.