Tempus Timing Solution | Cadence

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Overview

Industry’s Fastest Adopted and Trusted Signoff Solution for FinFET Designs

The Cadence Tempus Timing Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry, providing faster design closure turnaround time while delivering the best-in-its-class power, performance, and area (PPA). Customers trust innovative Tempus capabilities such as SmartScope, CMMMC, Design Robustness Analysis, SmartMMMC Optimization, etc. to optimize and signoff their most complex, large, and complicated designs at advanced nodes.

The Tempus solution is deeply integrated with Cadence’s Innovus Implementation System, Quantus Extraction Solution, and Voltus IC Power Solution to deliver the best user experience during the entire design cycle.

cube design

Key Benefits

Advantages of Empowering Design Teams Through Productivity Boosts

Better PPA

Optimized for better PPA and signoff closure while employing AI

Improved Productivity

Industry’s fastest runtimes on a single machine or in the cloud with 5X faster runtime with CMMMC technology

Foundry Certified

Fully certified down to 3nm

Familiar User Interface

Streamlines flow development and simplifies user trainings with new common user interface shared across the Cadence digital full flow

Features

Faster Design Closure Turnaround Time While
Delivering the Best-In-Its-Class Power

Tempus ECO

Physically aware timing and power optimization
Speed design closure time by 3X with best PPA
Fewest iterations provides most convergent ECO
Save up to 5% dynamic power
Common signoff engines used for faster convergence

Mixed Signal diagram

Customer Stories

See What Customers Have to Say About the Tempus Timing Solution

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

Michael Jackson, Corporate VP of R&D at Cadence, explains why customers are adopting the Tempus Solution and how they achieve 2X faster time-to-signoff closure with the best power, performance, and area.

Maxlinear

Maxlinear uses Tempus ECO and Tempus Signoff in an Innovus flow to reduce overall design closure time and achieve better PPA.

Blu Wireless

Customer success story of Inphi reducing time to market taping out 7nm full chip flat with Tempus Timing Signoff

Inphi

Customer success story of Inphi reducing time to market taping out 7nm full chip flat with Tempus Timing Signoff

SiFive

Discover how SiFive used Cadence tools to achieve better PPA and faster design closure time

Signoff

DSTA

Production-proven capacity to time over 1B instances flat with unique DSTA for full chip signoff
Tempus DSTA distributes STA across smaller-memory machines
Same accuracy as single-machine STA
Ideal for cloud deployment
Same look and feel and easily integates into existing STA flow

DSTA diagram

SmartScope

Faster runtime and reduced memory with hierarchical abstraction and boundary models
Timing closure on multiply-instanced modules
Provide same accuracy as flat STA
Facilitates parallel closure of block and top-level

SmartScope diagram

Design Robustness Analysis Applications

Aging-Aware STA

Breakthrough technology to address aging problem for automotive, aerospace, consumer, mobile, and hyperscale designs with Liberate Characterization Solution and Tempus
Consumes aging libraries, that supports various stress conditions and recovery, generated by Liberate Characterization Solution
SPICE-accurate aging analysis capability for long-term reliability with better PPA
Address instance-specific and non-uniform aging (aging context can be different than STA condition)
Accurate analysis leading to avoiding over design and improve PPA

Tempus Power Integrity (PI)

Breakthrough technology in providing true-signoff solution
Seamless Tempus and Voltus integration to provide next-generation IR drop analysis and fixing technology
Catching timing violations missed by today’s traditional IR-drop signoff methodology resulting in dead silicon
Automated fixing by Tempus ECO the IR drop issues by optimizing both the victim and aggressor paths
Reduce max IR-drop design margin and achieving best PPA

Timing Robustness

Statistical measure of silicon performance
Mathematically model design robustness using LVF libs
Meet reliability targets (ex. 4-sigma) while significantly improving (by several %) design PPA

Customer Stories

See What Customers Have to Say About the Tempus Timing Solution

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

Michael Jackson, Corporate VP of R&D at Cadence, explains why customers are adopting the Tempus Solution and how they achieve 2X faster time-to-signoff closure with the best power, performance, and area.

Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack

Integrity 3D-IC is Cadence’s next-generation multi-chip design solution, integrating silicon and package planning and implementation with system analysis and signoff to enable system-driven PPA optimization.

Arm Neoverse CPU Advanced Timing Signoff with Tempus™ PI Technology

As part of Neoverse CPU design, Arm is using Tempus-PI, an integrated IR drop/STA solution, combining the accuracy and speed of Tempus STA with Voltus IR drop analysis.

IR & Timing Co-Signoff Based on Tempus

Design challenge with IR signoff closure

Accelerating the Timing Signoff for Large SoC Designs

Leveraging Boundary Model in Tempus Timing Signoff Solution

Mixed-Signal STA

Supports mixed-signal design through integration with Virtuoso Open Access database

Mixed Signal diagram

Customer Stories

See What Customers Have to Say About the Tempus Timing Solution

Mixed-Signal STA

A Novel Methodology to Signoff in a Complex Mixed Signal SoC

Resources

Browse Recommended Resources

Tempus Power Integrity “True Signoff”

Maxlinear Signing-Off using Tempus with Confidence for FinFET Designs

Managing Signoff Corners with MMMC Flows

Mixed Signal STA Webinar

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

white paper

Intelligently Managing 3D-IC Timing Signoff

White Paper

Hierarchical Timing Analysis: Pros, Cons, and a New Approach

Datasheet

Tempus Timing Signoff Solution

Video

Signoff STA for Multi-Chiplet Design

News

Cadence Digital and Custom/Analog Design Flows Achieve Certification for TSMC’s Latest N4P and N3E Processes

25 Oct 2022
News Release

Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success

28 Jun 2022
News Release

Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes

13 Jun 2022
News Release

Blogs

Quantus Extraction Solution

The linchpin that allows designers to do more with Rs and Cs on both digital- and transistor-level flows, assuring on-time tapeout

Voltus IC Power Integrity Solution

A standalone, cloud-ready, full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization on a PDN or power grid of a chip

Innovus Implementation System

Optimized for the most challenging designs at the latest FinFET 16nm, 14nm, 7nm, and 5nm processes to help designers get an earlier design start with a faster ramp-up

Voltus-Fi Custom Power Integrity Solution

A transistor-level electromigration and IR drop (EM-IR) tool that delivers foundry-certified SPICE-level accuracy in power signoff

Virtuoso Layout Suite

Supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels