Tempus Timing Signoff Solution

The Cadence^® Tempus^™ Timing Signoff Solution is the fastest static timing analysis (STA) tool in the industry today with unique distributed processing and cloud capabilities enabling hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution is delivering SPICE-accurate results to hundreds of customers across a broad range of design types: from the largest 5nm designs, to high-volume mobile designs, and mixed-signal chips on mature processes.

The Tempus solution is a modern tool designed to tackle the most advanced timing requirements including full signal integrity (SI) analysis, statistical on-chip variation (SOCV), multi-mode and multi-corner (MMMC) analysis, static- and dynamic-power reduction, and hierarchical timing models.

More than just an analysis tool, the Tempus solution is also deeply integrated with Cadence’s Innovus^™ Implementation System and Voltus^™ IC Power Solution.

Distributed Processing and Multi-Threading

Every Tempus timing job is naturally multi-threaded for faster execution on 16 CPUs and more. But as designs get larger it is no longer feasible to buy ever bigger, expensive TB memory machines to run STA. The Tempus solution has the unique capability to distribute an STA job across multiple, separate computers to deliver significantly faster runtimes and less memory per machine. Distributed STA (DSTA) allows you to perform full-chip flat STA signoff on huge designs of over 1 billion instances on a set of normal memory machines with just 256GB of memory. And because there is no hierarchical modeling involved, there is no loss of accuracy compared to single-machine STA. Distributed STA is a scalable solution for the huge design sizes of tomorrow and ideal for execution in the cloud.

Tempus ECO Integration with Innovus Implementation

The Innovus and Tempus solutions share the same timing engine, so it is not only convenient but improves correlation when you optimize your design with the Tempus ECO option. Tempus ECO is physically aware and shares Innovus implementation’s placement engine so that inserted cells are always fully legally placed and don’t need to be moved by legalization in the Innovus system—avoiding timing surprises after ECO.

The excellent correlation, integrated menus inside Innovus implementation, and advanced power and timing optimization algorithms speed timing closure by 2X over disjoint flows.

Tempus ECO fixes setup, hold, glitch, and design rule violations and will optimize your design for dynamic power, leakage power, or total power.

Tempus Power Integrity Integration with Voltus Solution for STA-Aware IR Drop

Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity option integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, Tempus ECO will automatically fix IR drop issues by optimizing both the victim and aggressor paths.

CMMMC

The Tempus solution offers unique concurrent multi-mode multi-corner (CMMMC) technology to process MMMC views concurrently in a single STA job. CMMMC exploits the commonalities between views to deliver a 5X faster runtime without any loss in accuracy, which means you can run the same number of signoff corners with fewer machines and less time.

SI Analysis

Every Tempus license includes a complete SI analysis engine that calculates all cross-talk interactions with relevant timing windows. Glitch analysis and glitch propagation are also supported.

Power Analysis

The Tempus solution will report the dynamic and static power used by a circuit. This calculation can be performed with user-supplied activity files or vectorless activity profiles.

SOCV

The Tempus solution offers statistical on-chip variation (SOCV) to reduce unwarranted pessimism caused by on-chip variation. The Tempus solution supports both the Cadence SOCV library format and the Liberty Variation Format (LVF) for statistical library characterization. The Tempus solution can also accurately model and calculate the ultra-low voltage effects at 5nm and below that cause the statistical variation to be non-symmetrically skewed about the mean (third moment).

Hierarchical Models and SmartScope

The Tempus solution offers a range of sophisticated hierarchical modeling options beyond traditional extracted timing models (ETM) and interface logic models (ILM). To facilitate signoff-accurate hierarchical STA, the Tempus solution has introduced high-accuracy proprietary boundary models for block abstraction when optimizing the top level. And, for block-level optimization, the Tempus solution supports both context models and BlockScope models to capture top-level context for block optimization. These hierarchical models capture far more detail than traditional models, including SI aggressors, signal waveforms, clock latency, and advanced OCV (AOCV) stage count on the pins.

Common User Interface

A new common user interface is shared with the Innovus, Voltus, and Tempus solutions to streamline flow development and simplify user trainings across a complete Cadence digital full flow.

Integration with Virtuoso Platform

The Tempus solution is available within Cadence’s Virtuoso^® custom design platform through seamless data integration with its Open Access database as part of the Virtuoso Digital Signoff package for small embedded digital logic in mixed-signal designs. It includes cross-probing of timing paths between a timing report and the Virtuoso layout editor, automatic abstraction of digital components, parasitic extraction, and SDC integration.