Home
  • Products
  • Solutions
  • Support
  • Company
  • EN US
    • SELECT YOUR COUNTRY OR REGION

    • China - 简体中文
    • Japan - 日本語
    • Korea - 한국어
    • Taiwan - 繁體中文

DESIGN EXCELLENCE

  • Digital Design and Signoff
  • Custom IC
  • Verification
  • IP
  • IC Package

SYSTEM INNOVATION

  • Multiphysics System Analysis
  • Embedded Software
  • PCB Design
  • Computational Fluid Dynamics

PERVASIVE INTELLIGENCE

  • AI / Machine Learning
  • AI IP Portfolio

CADENCE CLOUD

VIEW ALL PRODUCTS

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test

FEATURED PRODUCTS

  • Integrity 3D-IC Platform
  • Cadence Cerebrus Intelligent Chip Explorer
  • Genus Synthesis Solution
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Voltus IC Power Integrity Solution
  • Pegasus Verification System
  • RESOURCES
  • Flows

Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

PRODUCT CATEGORIES

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
  • Spectre FX Simulator
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus-XFi Custom Power Integrity Solution
  • RESOURCES
  • Flows

Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

  • Debug Analysis
  • Virtual Prototyping
  • Emulation and Prototyping
  • Static and Formal Verification
  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP

FEATURED PRODUCTS

  • vManager Verification Management
  • Jasper C Apps
  • Helium Virtual and Hybrid Studio
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • RESOURCES
  • Flows

IP

An open IP platform for you to customize your app-driven SoC design.

PRODUCT CATEGORIES

  • 112G/56G SerDes
  • Chiplet and D2D
  • Denali Memory Interface and Storage IP
  • Interface IP
  • PCIe and CXL
  • Tensilica Processor IP

RESOURCES

  • Discover PCIe

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

PRODUCT CATEGORIES

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • Flows

Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Computational Fluid Dynamics
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Signal and Power Integrity
  • Thermal Solutions

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Solver Cloud
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Fidelity CFD
  • Sigrity Advanced SI
  • Celsius Advanced PTI
  • RESOURCES
  • System Analysis Center
  • System Analysis Resources Hub
  • AWR Free Trial

Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • RF / Microwave Design
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
  • Allegro PCB Designer
  • Allegro X Design Platform
  • RESOURCES
  • What's New in Allegro
  • Advanced PCB Design & Analysis Resources Hub
  • Flows

Computational Fluid Dynamics

AI / Machine Learning

AI IP Portfolio

Industries

  • 5G Systems and Subsystems
  • Aerospace and Defense
  • Automotive
  • Hyperscale Computing

Technologies

  • 3D-IC Design
  • Advanced Node
  • AI / Machine Learning
  • Arm-Based Solutions
  • Cloud Solutions
  • Computational Fluid Dynamics
  • Functional Safety
  • Low Power
  • Mixed Signal
  • Photonics
  • RF / Microwave
Designed with Cadence See how our customers create innovative products with Cadence

Support

  • Support Process
  • Online Support
  • Software Downloads
  • Computing Platform Support
  • Customer Support Contacts
  • Technical Forums

Training

  • Custom IC / Analog / RF Design
  • Languages and Methodologies
  • Digital Design and Signoff
  • IC Package
  • PCB Design
  • System Design and Verification
  • Tensilica Processor IP
Link for support software downloads Stay up to date with the latest software
24/7 - Cadence Online Support Visit Now

Corporate

  • About Us
  • Designed with Cadence
  • Investor Relations
  • Leadership Team
  • Computational Software
  • Alliances
  • Corporate Social Responsibility
  • Cadence Academic Network
  • Intelligent System Design

Culture and Careers

  • Culture and Diversity
  • Careers

Media Center

  • Events
  • Newsroom
  • Blogs
Cadence Giving Foundation
Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • Support
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
  • Company
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
        • Intelligent System Design
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
        • Intelligent System Design
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
        • Intelligent System Design
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Media Center
        • Events
        • Newsroom
        • Blogs

Tempus Timing Signoff Solution

Industry’s fastest-adopted and trusted timing signoff solution for FinFET designs

Read Datasheet Read White Paper
  • Overview
  • Videos
  • News and Blogs
  • Customers
  • Support and Training

The Cadence® Tempus™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types, from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.

More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, and Voltus™ IC Power Solution.

Key Benefits

  • Industry’s fastest runtimes on a single machine or in the cloud
  • 5X faster runtime with CMMMC technology
  • Fully certified down to 3nm
  • Streamline flow development and simplify user trainings with new common user interface shared across the Cadence digital full flow
  • Accurate modeling of ultra-low voltage effects below 0.5V with advanced SI and SOCV, supports both Cadence SOCV library format and Liberty Variation Format (LVF)
ASK US A QUESTION

 

Tempus diagram

Design Robustness

Cadence is focused on innovating in partnership with the industry’s most advanced companies to create even-greater design advantage and shorten time to market with best-in-class power, performance, and area (PPA).

One key aspect of interest to our customers is design robustness and its tradeoff with PPA. Design robustness is a six-prong approach to providing the highest quality of designs via Cadence’s suite of analysis tools—namely ultra-low Vdd robustness, aging robustness (aging-aware STA),voltage robustness (Tempus Power Integrity solution), process robustness (timing robustness), VT robustness, and interconnect robustness.

  1. Aging-Aware STA with Liberate Characterization Solution

    High-reliability semiconductor applications such as automotive and defense must operate predictably over long timespans. To ensure high reliability, designers require accurate analysis of device performance over time without relying on pessimistic margining techniques that negatively impact PPA. To solve this problem, our unified flow, starting from Liberate characterization through to Tempus STA and Tempus ECO, enables designers to accurately analyze aging effects in the context of their design. This improved accuracy, in turn, allows for a re-examination of margins and subsequent PPA savings.

  2. Tempus Power Integrity Solution with Voltus Solution for STA-Aware IR Drop

    Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity Solution integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

    Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, the Tempus ECO Option will automatically fix IR drop issues by optimizing both the victim and aggressor paths.

  3. Timing Robustness

    Timing robustness is the statistical measure of chip performance. It co-exists with conventional signoff slack analysis and provides a complimentary metric to slack analysis for use during Tempus ECO optimization. Its key benefit is to ensure high reliability while avoiding unnecessary over-design and delivering improved PPA.

Stay Connected

We’ll keep you up to speed on the latest Digital Design and Signoff tips, insights, and developments.

Subscribe

Contact Us

TRAINING COURSES

Breakthrough Aging-Aware STA
Watch Now
Download Story
Blu Wireless Accelerates 5G mmWave Design Tapeout

Learn how Blu Wireless used the Tempus Solution to overcome design challenges and meet aggressive tapeout schedule

ShareLink Copied

Cadence Tempus Update Promises to Transform Timing Signoff User Experience

Shortening time to market with best-in-class PPA

READ ARTICLE
Download story
SiFive Tapeout FinFET Products Using Tempus ECO and Signoff

Discover how SiFive used Cadence tools to achieve better PPA and faster design closure time

ShareLink Copied

Customers Tape Out Using Tempus ECO and Signoff with Working Silicon
READ ARTICLE
  • Related Links

    • Mixed-Signal Implementation
    • Digital Advanced Node
    • Tempus Delivering Faster Timing Signoff with Optimal PPA
    • Inphi Reduces Time to Market with 2X Turnaround Time Reduction
    • Cadence Defines a New Signoff Paradigm with Tempus PI
    • Barefoot Networks Accelerates Timing Closure with Cloudburst Platform and Tempus Timing Signoff
  • Related Products

    • Quantus Extraction Solution
    • Voltus IC Power Integrity Solution
    • Innovus Implementation System
    • Voltus-Fi Custom Power Integrity Solution
    • Virtuoso Layout Suite

Resources

white paper

Intelligently Managing 3D-IC Timing Signoff

White Paper

Hierarchical Timing Analysis: Pros, Cons, and a New Approach White Paper

Download Now

Datasheet

Tempus Timing Signoff Solution

Download Now

Video

Signoff STA for Multi-Chiplet Design

Watch Now
View All
Videos

Tempus Power Integrity “True Signoff”

Maxlinear Signing-Off using Tempus with Confidence for FinFET Designs

Managing Signoff Corners with MMMC Flows

Mixed Signal STA Webinar

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

News ReleasesVIEW ALL
  • Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success 06/28/2022

  • Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes 06/13/2022

  • Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms 05/19/2022

  • Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud 12/01/2021

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

Blogs VIEW ALL
Customers

The Tempus Timing Signoff Solution has been our timing tool for all of our SoCs that enable smart TV, set-top boxes and media connectivity. Its runtime performance, coupled with integration within the Cadence Innovus™ Implementation System, has allowed us to significantly reduce the time we spend in timing signoff.

Jacques Martinella, Vice President, Engineering, Sigma Designs

Read More or View All Customers

The size and complexity characteristics of our latest design required a timing solution that could handle more than 50M cells quickly and efficiently. We determined that the Tempus Timing Signoff Solution was the right timing platform to address our signoff analysis and closure needs.

Toru Hiyama, General Manager for Platform Advanced Engineering Operation, Information and Telecommunication System Company, Hitachi, Ltd.

Read More or View All Customers

The Tempus Timing Signoff Solution has enabled us to complete several successful tapeouts of our datacenter interconnect solutions. We were able to effectively use the tool for distributed multi-mode, multi-corner (MMMC) timing analysis and closure to get our products out the door and into the fab.

Lawrence Tse, Vice President of Engineering, Inphi

Read More or View All Customers

Support

Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview

Cadence Online Support

  • Details about online supportLearn more

  • Have an account already?Log in

  • New to support?Sign up

  • Online support overview Link to video

Customer Support

  • Support Process
  • Software Downloads
  • Computing Platform Support
  • University Software Program
  • Customer Support Contacts
Training

Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview

Course Delivery Methods

  • Instructor-Led Training
  • Online Training
  • Get Cadence Certified

Regional Training Information

  • China
  • Europe, Middle East, and Africa
  • India
  • Japan
  • Korea
  • North America
  • Singapore
  • Taiwan
Fortune 100 Best Companies to Work for 2022

A Great Place to Do Great Work!

Eighth year on the FORTUNE 100 list

Our Culture Join The Team
  • Products
  • Custom IC and RF
  • Digital Design and Signoff
  • IC Package
  • IP
  • PCB Design
  • System Analysis
  • Verification
  • All Products
  • Company
  • About Us
  • Leadership Team
  • Investor Relations
  • Alliances
  • Careers
  • Cadence Academic Network
  • Supplier
  • Media Center
  • Events
  • Newsroom
  • Designed with Cadence
  • Blogs
  • Forums
  • Glossary
  • Contact Us
  • Send Us A Message
  • Customer Support
  • Media Relations
  • Global Office Locator

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2022 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • US Trademarks
  • Do Not Sell My Personal Information