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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
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      • AI IP Portfolio
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Tempus Timing Signoff Solution

Industry’s fastest-adopted and trusted timing signoff solution for FinFET designs

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Key Benefits

  • Achieve industry’s fastest runtimes on a single machine or in the cloud
  • Capacity to time over 1B instances flat with unique DSTA for full-chip signoff
  • Speed design closure time by 3X and save up to 5% dynamic power Tempus ECO tightly integrated with Innovus Implementation System for physically aware timing and power optimization
  • Find IR drop failures missed by traditional flows at 7nm and below with Tempus Power Integrity’s STA-aware IR drop analysis
  • ​Fully certified down to 3nm​
  • 5X faster runtime with CMMMC technology
  • Streamline flow development and simplify user trainings with new Common User Interface shared across the Cadence digital full flow
  • Accurate modeling of ultra-low voltage effects below 0.5V with advanced SI and SOCV; supports both Cadence SOCV library format and Liberty Variation Format (LVF)
  • Faster runtime and reduced memory with SmartScope hierarchical abstraction and boundary models providing the same accuracy as flat STA
  • Supports mixed-signal design through integration with Virtuoso Open Access database
ASK US A QUESTION

 

The Cadence® Tempus™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry today with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types: from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.

The Tempus solution is designed to tackle the most advanced timing requirements including full signal integrity (SI) analysis, glitch analysis and propagation, statistical on-chip variation (SOCV), multi-mode and multi-corner (MMMC) analysis, static and dynamic power reduction, and hierarchical timing models.

More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, and Voltus™ IC Power Solution.

Tempus Power Integrity Integration with Voltus Solution for STA-Aware IR Drop

Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity option integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, Tempus ECO will automatically fix IR drop issues by optimizing both the victim and aggressor paths.

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TRAINING COURSES

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

Blu Wireless Accelerates 5G mmWave Design Tapeout
LEARN MORE
Inphi Reduces Time to Market with 2X Turnaround Time Reduction
LEARN MORE
SiFive Tapeout FinFET Products Using Tempus ECO and Signoff
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Customers tapeout using Tempus ECO and Signoff with working silicon!
Read Article
  • Related Links

    • Mixed-Signal Implementation
    • Digital Advanced Node
    • Tempus Delivering Faster Timing Signoff with Optimal PPA
    • Cadence Defines a New Signoff Paradigm with Tempus PI
    • Barefoot Networks Accelerates Timing Closure with Cloudburst Platform and Tempus Timing Signoff
  • Related Products

    • Quantus Extraction Solution
    • Voltus IC Power Integrity Solution
    • Innovus Implementation System
    • Voltus-Fi Custom Power Integrity Solution
    • Virtuoso Layout Suite
Videos

Tempus Power Integrity “True Signoff”

Maxlinear Signing-Off using Tempus with Confidence for FinFET Designs

Managing Signoff Corners with MMMC Flows

Mixed Signal STA Webinar

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

News ReleasesVIEW ALL
  • Cadence Collaborates with Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm 04/08/2021

  • Cadence Delivers Automotive Reference Flow for Samsung Foundry 14LPU Process Technology 04/08/2021

  • Cadence Wins Four 2020 TSMC OIP Partner of the Year Awards 11/02/2020

  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

Blogs VIEW ALL
Customers

The Tempus Timing Signoff Solution has been our timing tool for all of our SoCs that enable smart TV, set-top boxes and media connectivity. Its runtime performance, coupled with integration within the Cadence Innovus™ Implementation System, has allowed us to significantly reduce the time we spend in timing signoff.

Jacques Martinella, Vice President, Engineering, Sigma Designs

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The size and complexity characteristics of our latest design required a timing solution that could handle more than 50M cells quickly and efficiently. We determined that the Tempus Timing Signoff Solution was the right timing platform to address our signoff analysis and closure needs.

Toru Hiyama, General Manager for Platform Advanced Engineering Operation, Information and Telecommunication System Company, Hitachi, Ltd.

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The Tempus Timing Signoff Solution has enabled us to complete several successful tapeouts of our datacenter interconnect solutions. We were able to effectively use the tool for distributed multi-mode, multi-corner (MMMC) timing analysis and closure to get our products out the door and into the fab.

Lawrence Tse, Vice President of Engineering, Inphi

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