Voltus IC Power Integrity Solution

The Cadence^® Voltus^™ IC Power Integrity Solution is a standalone, full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies on a power delivery network (PDN) or the power grid of a chip. The Voltus tool is of particular value to designers by providing better understanding of the power grid strength, as well as debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations (EMIR). Typical use of the tool may include, but is not limited to: 

• Analysis of the full-chip resistance network, including instance-based effective resistance (Reff) and resistance of the least-resistance path (Rlrp) analysis
• Calculation and analysis of power consumption, including leakage, internal, and switching power
• Analysis and optimization of EM and IR drop, including full-chip signal EM (SEM)
• Analysis of the impact of power on design closure, from chip to package to PCB
• Analysis and optimization of ESD protection circuitry
• Analysis of advanced FinFET features such as self-heating effect (SHE) and statistical EM budgeting (SEB)/failure-in-time(FIT) calculations

Massively Parallel Execution for Large Capacity and High Performance

At the heart of the Voltus solution is its massively parallel execution algorithms that can run either multi-threaded on one single machine or distributed on multiple machines in a private- or public-cloud environment. The parallel execution applies to all major steps of a power signoff run—not only to the instance power calculation, grid network parasitic extraction, GUI display, etc., but also, more importantly, to the matrix solving in the highly coupled grid network simulation. Its unique correct-by-construction in SPICE-like matrix formation guarantees that the Voltus distributed-processing (Voltus-DP) solution has:

• Consistent and accurate results, regardless of the number of machines allocated
• Near-linear scalability in performance, memory footprint, and capacity as the number of CPUs/machines increases

Advanced Power Grid Simulation Technologies

To meet today’s design requirements, the Voltus solution supports various kinds of power grid network simulation methodologies and flows:

• Static analysis and dynamic analysis
• Vector-less analysis, including state-propagation algorithm
• Vector-based analysis, including gate/RTL-level VCD/FSDB, test scan-mode, etc.
• Physical-aware power-density (hot-spot) vector profiling
• Hybrid, mixed-mode analysis in the combination of gate/RTL vectors and vector-less
• Direct vector link to Cadence Palladium^® (PHY) and Xcelium^™ (SHM) platforms

Cadence Digital “Full-Flow” for Fast Design Closure and High-Quality Design

Beneficial as a standalone power signoff tool, the Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated “full-flow” environment with other key products, including the Cadence Innovus^™ Implementation System and the Cadence Tempus^™ Timing Signoff Solution, providing the industry’s fastest design closure technology. Such integration enables the interaction among P&R implementation, timing, and IR drop analysis that pulls the potential power signoff issues ahead into the design implementation stage. This allows early prevention, fixing, or optimization, avoiding often difficult and costly design fixes or changes at the signoff stage. Such popular features include:

• Early rail analysis (ERA) on an incomplete P&R design, as early as the floorplanning stage
• IR drop aware placement-driven hotspot fixing
• Timing-aware IR drop hotspot fixing with Tempus ECO
• Signal EM violation identification and fixing 
• Power grid optimization, including metal trimming and power gate switch trimming
• IR drop-aware Tempus STA in clock jitter analysis
• De-coupling cap analysis and optimization
• Power-gate switching analysis, including in-rush current and turn-on time 

Comprehensive Power Signoff Solutions for Analog Mixed-Signal SoC Designs

When used with the Cadence Voltus-Fi Custom Power Integrity Solution, a transistor-level EMIR tool delivering foundry-certified SPICE-level accuracy and power grid macro modeling, the resulting platform accelerates IC power signoff and overall design closure on an analog mixed-signal design:

• An integrated solution in the Cadence Virtuoso^® platform with the Quantus^™ QRC Extraction Solution for parasitic extraction and Spectre^® for EMIR simulation 
• Power-grid-view (PGV) macro modeling to enable a transistor block/IP analyzed in the Voltus solution for full-chip power signoff

Chip-Package-Board Co-Analysis 

When used with Cadence Sigrity^™ technologies, Voltus-Sigrity Package Analysis (Voltus-Sigrity PA) enables the accurate co-analysis of a power grid network on a chip-package-PCB system:

• Package model from the Sigrity XtractIM^™ tool for chip power signoff by the Voltus solution and die model from the Voltus solution for package power signoff from the Sigrity PowerDC^™ tool
• Power distribution on the chip from the Voltus solution for thermal distribution analysis by the PowerDC tool