The Cadence® Jasper™ RTL Apps feature machine learning technology and core formal technology enhancements.
The Jasper RTL Apps represent the latest stage of ongoing proof-solver algorithm and orchestration improvements. They incorporate Smart Proof technology to improve verification throughput, while machine learning is used to select and parameterize solvers to enable faster first-time proofs. Additionally, machine learning is used to optimize successive runs for regression testing, either on premises or in the cloud. With Smart Proof technology, proofs speed up on average by 2X out of the box and by 5X on regression runs.
Given today’s larger and more complex SoC designs, the design compilation process sets the maximum size of design, and the compute resources necessary, to start formal analysis. The Jasper RTL Apps deliver more than 2X design compilation capacity with an average of 50% reduction in memory usage during compilation. Additionally, engineers can effectively scale design capacity through advanced parallel compilation technologies that optimally use available compute resources and run proofs in the cloud.
Formal coverage technologies let engineers perform IP signoff purely within the Jasper RTL Apps. These formal signoff technologies include improved proof-core and checker coverage accuracy, techniques to derive meaningful coverage from deep bug hunting, and formal coverage analysis views. Ease your debug and what-if analysis with the powerful Jasper Visualize™ Interactive Debug Environment incorporating the QuietTrace™ debugging capability. Together, those features deliver signoff-quality formal coverage metrics and enable multi-engine chip-level verification closure.
Request white papers on formal verification for post-silicon debug, property synthesis, low power, register-transfer level (RTL) designer signoff, Superlint, and cache-coherent protocols.
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As long-time customers of Incisive formal and simulation solutions, we are impressed with the next-generation JasperGold platform. As well as improved debug and ease-of-use, we’ve achieved a significant increase in performance compared to Incisive Enterprise Verifier, as measured by proof convergence in a given time.
Mark Dunn, Executive Vice President, Imagination Technologies
"With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage.”
Hobson Bullman Vice President and General Manager, Technology Services Group, ARM
“We’ve identified functional and structural CDC issues earlier in the RTL signoff phase using the JasperGold CDC App. Eliminating these bugs earlier in the process has increased the quality of our designs and saved us between two and four weeks on the design and verification time for each of our IP.”
David Vincenzoni Design Manager at STMicroelectronics
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