Digital Design and Signoff Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
Silicon Signoff
- Basic Static Timing Analysis
- Cadence QRC RF Transistor and Substrate-level Extraction
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
Synthesis and Test
- Advanced Synthesis with Genus Stylus Common UI
- Advanced Synthesis with Genus Synthesis Solution
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Genus Synthesis Solution with Stylus Common UI
- Joules™ Power Calculator
- Low-Power Synthesis Flow with Genus Synthesis Solution (Libraries not included)
- Test Synthesis Using Genus Synthesis Solution
- Test Synthesis with Genus Stylus Common UI
- Virtuoso Digital Implementation
