- Cadence QRC RF Transistor and Substrate-level Extraction
- Conformal Equivalence Checking
- Encounter Conformal Constraint Designer (SDC/CDC Checks)
- Encounter Conformal ECO
- Genus Synthesis Solution With Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Low-Power Verification with Encounter Conformal
- Tempus Signoff Timing Analysis and Closure
- Voltus Power-Grid Analysis and Signoff
Digital Design and Signoff Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
Digital Design and Signoff
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus