Length : 1 day
Course Description
In this course, you use the Virtuoso® System Design Platform to generate a module level schematic that can be used to simulate an IC package as well as create the physical implementation. From the module level schematic you will generate a testbench symbol and testbench schematic for a pre-layout simulation and then transfer the module level schematic to SiP Layout for physical implementation. You will then run LVS and model the parasitics of the traces on the module. These models are then used on the testbench schematic to run a post-layout simulation of the IC in the context of the package.
Learning Objectives
After completing this course, you will be able to:
- Export cellviews from the VLE layout view
- Create a testbench schematic
- Run a pre-layout simulation of a module level schematic
- Export a module level schematic from VSE to SiP Layout for physical implementation
- Run LVS to verify that the Virtuoso schematic matches the SiP Layout physical implementation
- Extract S-parameter models for the parasitics of the traces on the physical implementation
- Run a post-layout simulation of the IC in the context of the module design
Software Used in This Course
- Virtuoso System Design Platform
- Virtuoso Schematic Editor XL
- Virtuoso Layout Suite XL
- Cadence SiP Layout XL
- XtractIM
- Spectre Multi Mode Simulation with AMS
Software Release(s)
IC617ISR19, SPB172ISR38, SPECTRE171, SIGRITY2017ISR9
Modules in this Course
- VSDP Pre-Layout Simulation
- VSDP Front To Back Flow
- EM Extraction
- Post-Layout Simulation
- VSDP Bottom-Up Flow
Audience
Prerequisites
You must have:
- A basic understanding of engineering design environments responsible for design, simulation and verification of Integrated Circuits and packaging of integrated circuits.
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
