Home
  • 技術產品
  • 解決方案
  • 支援與培訓
  • 公司資訊
  • ZH TW
    • SELECT YOUR COUNTRY OR REGION

    • US - English
    • China - 简体中文
    • Japan - 日本語
    • Korea - 한국어

DESIGN EXCELLENCE

  • 數位設計流程
  • 客製IC/類比/RF設計
  • Verification
  • IP
  • IC封裝設計與分析

SYSTEM INNOVATION

  • Multiphysics System Analysis
  • 嵌入式軟體
  • PCB設計與分析
  • Computational Fluid Dynamics

PERVASIVE INTELLIGENCE

  • AI / 機器學習
  • AI IP系列

CADENCE雲端方案

VIEW ALL PRODUCTS

數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test

FEATURED PRODUCTS

  • Cerebrus Intelligent Chip Explorer
  • Genus Synthesis Solution
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Pegasus Verification System
  • RESOURCES
  • Flows
  • Voltus IC Power Integrity Solution

客製IC/類比/RF設計

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

PRODUCT CATEGORIES

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
  • Spectre FX Simulator
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus-XFi Custom Power Integrity Solution
  • RESOURCES
  • Flows

系統設計與驗證

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

  • Debug Analysis
  • Virtual Prototyping
  • Emulation and Prototyping
  • Static and Formal Verification
  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP

FEATURED PRODUCTS

  • vManager Verification Management
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • RESOURCES
  • Flows
  • Jasper C Apps
  • Helium Virtual and Hybrid Studio

IP

An open IP platform for you to customize your app-driven SoC design.

PRODUCT CATEGORIES

  • Denali Memory Interface and Storage IP
  • 112G/56G SerDes
  • PCIe and CXL
  • Tensilica Processor IP
  • Chiplet and D2D
  • Interface IP

RESOURCES

  • Discover PCIe

IC封裝設計與分析

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

PRODUCT CATEGORIES

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • Flows

系統分析

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Computational Fluid Dynamics
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Signal and Power Integrity
  • Thermal Solutions

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Solver Cloud
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Fidelity CFD
  • Sigrity Advanced SI
  • Celsius Advanced PTI
  • RESOURCES
  • System Analysis Center
  • System Analysis Resources Hub
  • AWR Free Trial

嵌入式軟體

PCB設計與分析

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • RF / Microwave Design
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
  • Allegro PCB Designer
  • RESOURCES
  • What's New in Allegro
  • Advanced PCB Design & Analysis Resources Hub
  • Flows

Computational Fluid Dynamics

AI / 機器學習

AI IP系列

Industries

  • 5G 系統
  • 航太與國防
  • 車用方案
  • Hyperscale Computing

Technologies

  • 3D-IC 設計
  • 先進製程
  • AI / 機器學習
  • Arm-Based方案
  • Cloud Solutions
  • Computational Fluid Dynamics
  • Functional Safety
  • 低功耗方案
  • 混合訊號
  • Photonics
  • RF / Microwave
Designed with Cadence See how our customers create innovative products with Cadence

Support

  • Support Process
  • Online Support
  • Software Downloads
  • Computing Platform Support
  • Customer Support Contacts
  • Technical Forums

Training

  • Custom IC / Analog / RF Design
  • Languages and Methodologies
  • Digital Design and Signoff
  • IC Package
  • PCB Design
  • System Design and Verification
  • Tensilica Processor IP
Link for support software downloads Stay up to date with the latest software
24/7 - Cadence Online Support Visit Now

Corporate

  • About Us
  • Designed with Cadence
  • Investor Relations
  • Leadership Team
  • Computational Software
  • Alliances
  • Corporate Social Responsibility
  • Cadence Academic Network
  • Intelligent System Design

Culture and Careers

  • Culture and Diversity
  • Careers

Media Center

  • Events
  • Newsroom
  • Blogs
Cadence Giving Foundation
Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
ZH - Taiwan
  • US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
    • VIEW ALL PRODUCTS
  • 解決方案
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
  • 支援與培訓
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
  • 公司資訊
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
        • Intelligent System Design
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
        • Intelligent System Design
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
        • Intelligent System Design
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Media Center
        • Events
        • Newsroom
        • Blogs

  • Home
  •   :  
  • Training
  •   :  
  • All Courses
  •   :  
  • Genus Synthesis Solution With Stylus Common UI



Genus Synthesis Solution With Stylus Common UI

Instructor-Led Schedule
日期 版本 國家/地區 位置
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

In this course, you learn about the features of the Cadence® Genus™ Synthesis Solution with Stylus Common UI with next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture-level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools in the Genus Stylus CUI. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files.

You also learn how to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power using the Stylus Common UI. You will learn to query the design database and set attributes for synthesis flow in the Genus Stylus CUI. You explore Multi Mode Multi Corner (MMMC) Synthesis Flow in Genus. You also identify Flowkit and Unified Metrics capabilities.

Learning Objectives

After completing this course, you will be able to:

  • Explore the features of the Genus Stylus Common User Interface
  • Apply the recommended synthesis flow using the Cadence Genus Synthesis Solution
  • Explore MMMC and how to set up and update the MMMC configuration of a design
  • Debug design scenarios
  • Use the extended datapath features
  • Optimize designs using the physical synthesis flow
  • Analyze and synthesize the design for low-power structures
  • Constrain the design for testability (DFT)
  • Identify the interface to Conformal® equivalence checker and other tools
  • Explore Flowkit and Unified Metrics

Software Used in This Course

  • Genus Synthesis Solution

Software Release(s)

Genus 19.1

Modules in this Course

  • Overview of Genus Synthesis Solution Stylus Common UI
  • Getting Started with Genus Synthesis Solution
  • Working in Genus Shell
  • Synthesis Flow in Genus
  • Finding Information in the Genus Design Hierarchy
  • Exploring Genus Stylus Common UI GUI (Optional)
  • Editing the Netlist
  • Reducing Runtime
  • MMMC Flow
  • Debug Design Scenarios
  • Datapath Synthesis
  • Genus Physical Synthesis
  • Low-Power Optimization
  • Test Synthesis
  • Interfacing with LEC and Other Tools
  • FlowKit and Unified Metrics (Optional)

Audience

  • ASIC Designers
  • Digital IC Designers
  • Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Any HDL such as Verilog (recommended) or VHDL
  • Synthesis and ASIC design flow basics
  • Static Timing Analysis

Or you must have completed the following courses:

  • Basic Static Timing Analysis
  • Verilog Language and Application

Related Courses

  • Genus Synthesis Solution
  • Logic Equivalence Checking with Conformal EC
  • Innovus Digital Implementation (Block)
  • Innovus Digital Implementation (Hierarchical)

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86220

CONTACT TRAINING

ONLINE TRAINING
Genus Synthesis Solution v16.1

This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus

COURSE DETAILS

NEW COURSE
Mixed-Signal Simulation Using Spectre AMS Designer

GET DETAILS

 
 

"Interesting course."

Roger Cook, u-blox

"The instructor was really helpful and enthusiastic."

George Athanasiou, u-blox

"It is an excellent course. The new environment is amazing."

Nikos Georgoulopoulos, Aristotle University of Thessaloniki

 
 
Fortune 100 Best Companies to Work for 2022

A Great Place to Do Great Work!

Eighth year on the FORTUNE 100 list

Our Culture Join The Team
  • Products
  • Custom IC and RF
  • Digital Design and Signoff
  • IC Package
  • IP
  • PCB Design
  • System Analysis
  • Verification
  • All Products
  • Company
  • About Us
  • Leadership Team
  • Investor Relations
  • Alliances
  • Careers
  • Cadence Academic Network
  • Supplier
  • Media Center
  • Events
  • Newsroom
  • Press Releases
  • Designed with Cadence
  • Blogs
  • Forums
  • Glossary
  • Contact Us
  • General Inquiry
  • Customer Support
  • Media Relations
  • Global Office Locator

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2022 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • US Trademarks