Length : 1/2 day
Quantus Extraction Solution – RLCK Extraction You Trust
For classroom delivery, this course is taught as a half-day session (4 hours).
The course is designed to offer user-level experience on the next generation parasitic extraction solution from Cadence®–Quantus™ Extraction Solution.
You start with exploring the advanced node design solutions in Quantus. You will analyze extraction challenges in FINFETs, 3D-IC and Double/Multiple Patterning (DPT/MPT) designs and respective Quantus Extraction Solutions. You will also check the pros and cons of colored and colorless extraction flows with pessimism reduction. You will then performQuantus-based 7nm DPT Modeling, Shift Corners flows and explore 3D-IC Designs with TSV and Micro-Bumps. Finally, you will review the Transistor-Level EMIR Analysis flow with Voltus™-Fi Custom Power Integrity Solution and its advanced features.
The Quantus Extraction Solution is integrated in the Virtuoso® environment for easy access.
After completing this course, you will be able to:
- Discuss Advanced Node (FinFET and DPT) Design and Extraction challenges
- Check how Quantus addresses Advanced node Extraction challenges
- Explore Fin Shapes Formation and Layer Mapping with Quantus
- Analyze Diffusion Stretching and ICT File syntax for the FinFET process
- Explore the Fully Colored Design flow – emphasis on MPT, Decomposition and Pessimism Reduction
- Check the Quantus-based 7nm DPT Modeling and Shift Corners flows
- Examine Quantus support for HPB Airgap Dielectrics
- Explore Quantus-based extraction flows for 3D-IC Designs with TSV and Micro-Bumps
- Evaluate Comprehensive Quantus Integration to the Virtuoso platform
- Review the Transistor-Level EMIR Analysis flow with Voltus-Fi Custom Power Integrity Solution
- Explore the advanced features in Voltus-Fi-XL
Software Used in This Course
Virtuoso Layout Suite, Physical Verification System, Quantus Extraction Solution, Voltus-Fi Custom Power Integrity Solution
IC617, PVS16.2, EXT18.1
Modules in this Course
Quantus Advanced Node Features, Post-Layout Simulation and EMIR Analysis with Voltus-Fi-XL
- Physical Verification and Extraction engineers who need to address parasitic issues in their advanced node designs
You must have:
- Knowledge and experience with physical design, verification and extraction
- Familiarity with the Virtuoso Layout Suite
- Familiarity with basic concepts of design parasitics, EMIR effects and simulation
Quantus Transistor-Level T1: Overview and Technology Setup, Quantus Transistor-Level T2: Parasitic Extraction, Virtuoso Layout Design Basics, Physical Verification System, Assura® Parasitic Extraction (RCX), Cadence QRC Techgen Developer, Virtuoso Analog Design Environment, High-Performance Simulation Using Spectre Simulators