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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Computational Fluid Dynamics
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          • Signal and Power Integrity
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          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
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          • Celsius Advanced PTI
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          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
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          • Allegro PCB Designer
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          • Advanced PCB Design & Analysis Resources Hub
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        • 航太與國防
        • 車用方案
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  • Innovus Implementation System (Block)



Innovus Implementation System (Block)

Instructor-Led Schedule
日期 版本 國家/地區 位置
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length : 3 days

Digital Badge Available

Course Description

In this course, you learn how to use the Innovus™ Implementation System software to achieve the best power, performance and area (PPA) for your design. You learn several techniques for floorplanning and placement using the GigaPlace™ solver-based placement while implementing timing closure strategies with a multi-threaded, layer-aware timing and power-driven optimization engine to reduce dynamic and leakage power. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.

You run the slack-driven router with track-aware timing optimization which enables you to achieve the multiple objectives that are a part of today's design requirements. You will learn how to diagnose and fix routing violations as well as explore challenges and solutions for design implementation in nodes that are 20nm and below.

Other topics in this course include using database access commands, wire editing, metal fill, ECOs, and physical verification.

Learning Objectives

After completing this course, you will be able to:

  • Import and floorplan a design
  • Run placement and optimization using GigaPlace technology
  • Plan, route and analyze the power
  • Run timing analysis and debug results
  • Create clock trees and concurrently run datapath optimization
  • Run optimization for power, performance and area
  • Run the slack-driven router with track-aware timing optimization
  • Run global and detail routing for timing and signal integrity
  • Debug routing violations
  • Create and edit wires interactively
  • Run ECOs on a design
  • Address 20nm (and below) challenges as a result of Multi-Pattern Technology (MPT)
  • Run design verification for geometry, connectivity, antenna and metal fill
  • Run database access commands
  • Run Foundation Flow scripts

Software Used in This Course

  • Innovus Implementation System

Software Release(s)

INNOVUS191

Modules in this Course

  • Innovus Implementation System Overview
  • Design Import and Customizing the Innovus Implementation System Environment
  • Selecting and Highlighting Objects in the Design
  • Floorplanning the Design
  • Planning Power
  • Routing Power with Special Route
  • Running Placement Optimization
  • Scan Optimization and Reordering
  • Analyzing Route Feasibility with Early Global Route
  • Multi-Mode Multi-Corner Analysis
  • Extracting Parasitics and Running Timing Analysis
  • Power, Performance and Area Optimization
  • Implementing the Clock Tree
  • Detail Routing for Signal Integrity, Timing and Design for Yield
  • Wire Editing
  • Preventing and Fixing Signal Integrity Problems
  • Metal Fill
  • Verification
  • Engineering Change Orders
  • Writing Out a Design
  • Challenges of Advanced Nodes in Implementation
  • Innovus Database Access Commands
  • Foundation Flow Scripts

Audience

  • CAD Engineers
  • Chip Designers
  • Physical Layout Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Design methodology

Related Courses

  • Innovus Implementation System (Hierarchical)
  • Innovus Clock Concurrent Technology for Clock Tree Synthesis
  • Tempus Signoff Timing Analysis and Closure

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 86141

CONTACT TRAINING

ONLINE TRAINING
Genus Synthesis Solution v16.1

This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus

COURSE DETAILS

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“Everything was perfect. I'm very delighted I took part in it, it's incredibly useful to have a basic understanding of the whole flow.

Lots of useful suggestions for further projects in regards of software questions. Very well described lab manual.”

“The course was very interesting and useful."

Yossi Shlush, Sandisk

“Everything was fine, perfect level of knowledge/experience.”

„Overall useful course for a start in implementation - even for beginners“

Patrick Forster, Texas Instruments

"It was really well done and presented. Most of the topics are in line with what I am facing on a real challenging design. The training material was properly prepared by the trainers according to most of our requests, since most of us were already skilled on "basic" topics."

Lina Ferrari, STMicroelectronics

“I liked the pace of the course; the labs that followed each lecture/chapter and the chance to ask questions to the teacher. The course gave a good overview of the tools and some nice hands-on experience with the GUI. Very nice course and helpful instructor.”

Isac Jensen, Marvell

“Great intro to the tool, good instructor and learning environment.”

Michael Kesler

"(...)very complete, it covered all the expected topics."

Pablo Royer, ST Microelectronics

"Nice voice, very detailed slides and lots on info/tips." -Online Course-

Michele Lubrano Lobianco, ST Microelectronics

 
 
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