Join Cadence Training with Srdjan Djordjevic for a free, one-hour webinar.
Wednesday, March 18, 09:00 GMT / 10:00 CET
Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level
With double data rate (DDR) memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small challenge. Join Cadence Training and Srdjan Djordjevic, Sigrity Expert and Sr Principal Application Engineer, for our free one-hour webinar, Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level, where you will learn how to:
• Minimize DDR supply and DC drop at the PCB/package level
• Obtain the required DDR supply impedance profile over frequency, low enough and resonance free
• Perform SSN simulation of a DDR bus using power-aware IBIS models
• Plus Q&A