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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • 客製IC/類比/RF設計
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • 系統設計與驗證
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation and Testbench
        • Software-Driven Verification
        • Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC封裝設計與分析
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • Electromagnetic Solutions
        • RF / Microwave Solutions
        • Thermal Solutions
      • 嵌入式軟體
      • PCB設計與分析
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Solutions
        • Flows
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      • AI IP系列
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  • Allegro Sigrity SI Foundations

Allegro Sigrity SI Foundations

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Length: 2 days

Course Description

In this course, you use the Allegro® Sigrity™ SI software to develop design rules for high-speed designs. You add the resulting physical and electrical constraints to the design through topology templates. These constraints drive the routing of nets on the printed circuit board. You run preroute and postroute signal simulations to analyze the PCB for reflection, crosstalk, and other high-speed design factors.

Learning Objectives

After completing this course, you will be able to:

  • Create, extract and explore topologies
  • Run solution space analysis
  • Create an electrical constraint set
  • Apply constraints to drive placement and routing
  • Run postroute DRC check
  • Use template revision to update the ECSet applied to the nets
  • Analyze nets on the routed board design for signal integrity
  • Create estimated crosstalk constraints
  • Create a DesignLink between boards and use it to run multiboard simulation

Software Used in This Course

  • Allegro Sigrity SI Base

Software Release(s)

SPB17.2-2016QIR5

Modules in this Course

  • Introduction to Allegro Sigrity SI
  • Simulation Model Assignment
  • Topology Extraction
  • SigXplorer Basics
  • Sweep Simulations and Constraint Setting with SigXplorer
  • Constraint Floorplanning
  • DesignLink Creation
  • Postroute Analysis
  • Impedance and Coupling Checking
  • Estimated Crosstalk
  • Differential Pairs
  • The EMS2D Field Solver

Audience

  • Electrical Engineers
  • PCB Designers

Prerequisites

You must have

  • A familiarity with digital and analog circuit design methodology
  • A working knowledge of PCB signal analysis and transmission line theory

Related Courses

  • Allegro High-Speed Constraint Management
  • Allegro PCB Editor Intermediate Techniques

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 85073

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