Length : 5 days
Universal Verification Methodology (UVM) is the Accellera standard class-based verification library and reuse methodology for SystemVerilog. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology allows engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments. The course begins with a short review of SystemVerilog classes and class constructs, together with an overview of object-oriented concepts and features. The majority of the course describes a methodology for using the building blocks of the UVM class library to create configurable, reusable UVM Verification Components (UVCs) based on a standard architecture, and with embedded randomization, coverage, and self-checking. The course then shows you how to combine multiple UVCs into a flexible, powerful verification environment.
After completing this course, you will be able to:
Understand the features and capabilities of the UVM class library for SystemVerilog, Create and configure UVCs for your verification environments, Combine UVCs to implement a verification environment based on a proven methodology for creating reusable, scalable, and robust verification components.
Software Used in This Course
- XCELIUM1704, INCISIVE152
XCELIUM1704, INCISIVE 152
Modules in this Course
Day 1 - Essential SystemVerilog and Object-Oriented Design for UVM
Review of basic SystemVerilog classes, Polymorphism, virtual classes, and methods, Developing robust class methods, Class-based component hierarchy, Factory and builder design patterns
Days 2-5 – UVM Verification Environment
Introduction to UVM methodology and Universal Verification Component (UVC) structure, Overview of the router lab project, Stimulus modeling, Simulation phases, Creating a simple environment, Test classes, Configuration, Type Overrides and the Factory, UVM sequences, Connecting to a DUT, Interface and module UVCs, Multichannel sequences (virtual sequences), Building a scoreboard, Transaction-level modeling (TLM), Functional coverage modeling, Register Modeling in UVM, Conclusions
Lab exercises are structured around the verification of a real-life router design. The lab sessions include: Creating simple stimuli, Universal Verification Component (UVC) architecture, Factories and configuration control, Sequences, Integrating multiple UVCs, Writing multichannel and system-level tests, Building a scoreboard, TLM connections, Functional Coverage, Simple register modeling.
- Design engineers, Verification engineers
You must have:
- Experience with SystemVerilog. Review beforehand: Declaring and using class instances, including static members, Class inheritance and aggregation (composite classes), Class property randomization, Randomization constraints—relational, distribution, and conditional, Subprograms, including void functions