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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
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          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre FX Simulator
          • Virtuoso Layout Suite
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          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
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          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
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          • System Analysis Resources Hub
          • AWR Free Trial
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        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
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  • SKILL Programming for IC Layout Design



SKILL Programming for IC Layout Design

Instructor-Led Schedule
日期 版本 國家/地區 位置
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length : 2 days

Course Description

This advanced Engineer Explorer course provides a focused exploration of SKILL® programming in the Virtuoso® layout environment. You are required to have a working knowledge of SKILL programming and the Virtuoso Layout Editor or to complete the course prerequisites.

In this two-day course, you use the SKILL programming language to write code for layout design tasks for cell design, cell validation, library updates, and parameterized cells (Pcells). You also learn to

  • Run example SKILL programs to automate those tasks
  • Analyze key program constructs for each program
  • Customize the programs to meet new requirements
  • Explore options for enhancements to the programs

Learning Objectives

After completing this course, you will be able to:

Create and modify SKILL programs to

  • Measure cellview database objects (polygons, paths, rectangles) for area and capacitance
  • Hierarchically locate, highlight and report on I/O pads and cell locations
  • Compare pins and pin attributes on two cellviews and interface using a custom form
  • Copy a design and replace or update cell references in a design hierarchy
  • Analyze a Parameterized cell (Pcell) library to locate and update each Pcell, its associated parameters and Component Description Format (CDF) using a custom tabbed form

Software Used in This Course

SKILL development environment Virtuoso Layout Suites L

Software Release(s)

  • IC 6.1.6

Course Agenda

Day 1

Cell Design: Measuring Cellview Data

  • Run a program to report shape areas to reduce manual computations
  • Implement a table data structure to make programming easier
  • Create technology-independent code to reduce code maintenance
  • Add labels to improve usability

Cell Design: Locating I/O Cell Data

  • Run a program to locate instances of I/O cells based on cell names
  • Implement regular expression pattern matching to locate I/O cells
  • Enhance a program to determine the bond pad location at the top level

Cell Validation: Comparing Pins on Cellviews

  • Run a program to match pins on two different views of the same cell
  • Use a report field to display pin information
  • Modify the program to process all cells in a design hierarchy

Day 2

Library and Design Updates: Copying a Design and Replacing Cell References

  • Run the Library Manager copy utility
  • Reference sub cells to new masters to update the design
  • Run a SKILL program to copy, update references, and rename sub cells

Parameterized Cells: Analyzing Pcell Libraries

  • Look up Component Description Format (CDF) information for Pcell parameters
  • Display Pcell parameters with a tab field
  • Link to Pcell documentation with a hypertext field

Audience

Physical Layout Designers Cadence® Application Engineers Layout Designers CAD Developers CAD Engineers Cadence SKILL Programmers

 

Prerequisites

You must have the

  • Ability to develop or maintain SKILL programs

or you must have completed at least one the following courses:

  • SKILL Language Programming Introduction

  • SKILL Language Programming

Related Courses

  • SKILL Language Programming Introduction

  • SKILL Language Programming

  • Advanced SKILL Language Programming

  • Using Virtuoso Constraints Effectively

  • Virtuoso Layout Suites Update Training

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 84453

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"Most valuable in the course was not only learning new things but better ways of solving stuff I already tried myself on. Fluent and effective lecturer that responded swiftly also to issues somewhat outside the scope."

Lars Snith, Atmel

"Good course, good inputs and demo. Presentation style was very good."

Andreas Dost, Intel

 
 
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