Low-Power Verification with Encounter Conformal

After completing this course, you will be able to:

• Identify features of Conformal Low-Power software
• Identify the flows for low-power verification
• Identify power intent support in Conformal Low-Power software
• Apply low-power checks on gate netlists with corresponding power intent
• Apply low-power checks on physical netlists with corresponding power intent
• Run low-power equivalency checks in different stages along with the supplied power intent

• Conformal Low Power XL

• Overview
• Preparation and Setup
• Power Intent Support (CPF and IEEE 1801)
• Synthesis Verification
• Physical Verification
• Using Conformal Low-Power Effectively

• ASIC Designers
• Design Engineers
• Digital IC Designers
• FPGA Designers
• Hardware Engineers
• Logic Designers

You must have experience with or knowledge of the following:

• Have a basic understanding of Verilog language and constructs
• Have a basic understanding of one of the three CPF, UPF, or IEEE 1801 power intent formats
• Completed Logic Equivalence Checking with Conformal course or
• Have equivalent experience with the Conformal Equivalence Checker tool

Or you must have completed the following courses:

• Logic Equivalence Checking with Conformal EC

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.