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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
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  • Low-Power Verification with Encounter Conformal



Low-Power Verification with Encounter Conformal

Instructor-Led Schedule
日期 版本 國家/地區 位置
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length: 1 day

Course Description

In this course, you learn to verify low-power designs using Conformal® Low-Power Verification. In the labs, you debug practical examples of common power format (CPF) or IEEE 1801 violations, functional and structural violations, and nonequivalences.

Learning Objectives

After completing this course, you will be able to:

  • Identify features of Conformal Low-Power software
  • Identify the flows for low-power verification
  • Identify power intent support in Conformal Low-Power software
  • Apply low-power checks on gate netlists with corresponding power intent
  • Apply low-power checks on physical netlists with corresponding power intent
  • Run low-power equivalency checks in different stages along with the supplied power intent

Software Used in This Course

  • Conformal Low Power XL

Software Release(s)

CONFRML181

Modules in this Course

  • Overview
  • Preparation and Setup
  • Power Intent Support (CPF and IEEE 1801)
  • Synthesis Verification
  • Physical Verification
  • Using Conformal Low-Power Effectively

Audience

  • ASIC Designers
  • Design Engineers
  • Digital IC Designers
  • FPGA Designers
  • Hardware Engineers
  • Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

  • Have a basic understanding of Verilog language and constructs
  • Have a basic understanding of one of the three CPF, UPF, or IEEE 1801 power intent formats
  • Completed Logic Equivalence Checking with Conformal course or
  • Have equivalent experience with the Conformal Equivalence Checker tool

Or you must have completed the following courses:

  • Logic Equivalence Checking with Conformal EC

Related Courses

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 82156

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