Length : 4 days
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The Verilog Language and Application course offers a comprehensive exploration of the Verilog HDL and its application to ASIC and programmable logic design. The course provides a solid background in the use and application of the Verilog HDL to digital hardware design. This course covers all aspects of the language, from basic concepts and syntax through synthesis coding styles and guidelines to advanced language constructs and design verification. It also touches upon ASIC library design concepts.
After completing this course, you will be able to:
- Use fundamental Verilog constructs to create simple designs.
- Ensure that Verilog designs meet the requirements for synthesis.
- Develop Verilog test environments of significant capability and complexity.
Software Used in This Course
- Incisive® Enterprise Simulator XL and Encounter® RTL Compiler
- Incisive 15.1, RTL Compiler 14.25
Modules in this Course
- The first two days of the course cover the fundamental principles of the language and the constructs most commonly used in synthesizable Register Transfer Level (RTL) design.
- Problematic concepts such as blocking and nonblocking assignments are discussed in depth, and industry best-practice guidelines are presented.
- About the Course
- Describing Verilog Applications
- Language introduction
- Choosing Between Verilog Data types
- Using Verilog Operators
- Making Procedural Statements
- Making Blocking and Non-Blocking Assignments
- Using Continuous and Procedural Statements
- Understanding the Simulation Cycle
- Using Functions and Tasks
- Directing the Compiler
- Design Engineers
- Verification Engineers
You must have:
- The ability to navigate a file system and use a text editor.
- A basic understanding of digital hardware design and verification.
Prior experience with a procedural programming language is useful.
System Requirements for Online Courses
- For system requirements click here
- Cadence software as listed above installed and licensed
- Incisive SystemC, VHDL, and Verilog Simulation
- SystemVerilog Language and Application