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All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Custom IC / Analog / RF Design
- Abstract Generation
- Accelerate Design Productivity with Virtuoso ADE Explorer and Assembler
- Advanced SKILL Language Programming
- Analog Modeling with Verilog-A
- Assura DRC/LVS Rules Writer
- Assura Verification v3.1.7 (Classroom)
- Cadence QRC RF Transistor and Substrate-level Extraction
- Cadence QRC RF Transistor and Substrate-level Extraction
- Design Checks and Asserts
- Mixed Signal Simulations Using Spectre AMS Designer
- Pegasus Verification System
- Physical Verification System
- Quantus Transistor-Level T2: Parasitic Extraction
- Real Modeling with SystemVerilog
- Real Modeling with Verilog-AMS
- SKILL Development of Parameterized Cells
- SKILL Language Programming
- SKILL Language Programming Introduction
- SKILL Programming for IC Layout Design
- Spectre Accelerated Parallel Simulator
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Virtuoso ADE Assembler S1: Introducing the Assembler Environment
- Virtuoso ADE Assembler S2: Sweeping Variables, Simulating Corners, and Creating Run Plans
- Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator
- Virtuoso ADE Explorer S2: Analyzing Simulations Using the Virtuoso Waveform Tool
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso AMS Designer
- Virtuoso Abstract Generator
- Virtuoso Analog Design Environment
- Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T2 Create and Edit Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T5 Interactive Routing (XL)
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Advanced Nodes
- Virtuoso Layout for Advanced Nodes: T1 Place and Route
- Virtuoso Layout for Advanced Nodes: T2 Electromigration
- Virtuoso Online Training Course Collection
- Virtuoso Schematic Editor
- Virtuoso Space-Based Router Express
- Virtuoso Space-based Router
- Virtuoso Spectre RF
- Virtuoso Spectre RF
- Virtuoso System Design Platform
- Virtuoso Visualization and Analysis
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Digital Design and Signoff
- Advanced Synthesis with Genus Stylus Common UI
- Advanced Synthesis with Genus Synthesis Solution
- Basic Static Timing Analysis
- Cadence QRC RF Transistor and Substrate-level Extraction
- Conformal Equivalence Checking
- Conformal Low-Power Verification
- Custom Equivalence Checking with Conformal EC
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Genus Synthesis Solution with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Joules™ Power Calculator
- Tempus Signoff Timing Analysis and Closure
- Tempus Signoff Timing Analysis and Closure
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Test Synthesis Using Genus Synthesis Solution
- Test Synthesis with Genus Stylus Common UI
- Virtuoso Digital Implementation
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
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IC Package
- Allegro Package Designer
- Allegro Package Designer Plus
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity SI Foundations
- Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level (Webinar)
- Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
- OrbitIO System Planner
- Power Distribution Network Fundamentals for Design and PCB Layout (Webinar)
- SiP Layout
- SiP Layout
- Sigrity 1. Power Integrity Analysis - From DC to AC
- Sigrity 2. Power Aware Signal Integrity Analysis Part-I: For DDRx Analysis
- Sigrity 3. Power Aware Signal Integrity Analysis Part-II: For Serdes Analysis
- Sigrity PowerDC and OptimizePI
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
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Languages and Methodologies
- C++ Language Fundamentals for Design and Verification
- Essential SystemVerilog for UVM
- Real Modeling with SystemVerilog
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Assertions
- SystemVerilog Assertions
- SystemVerilog Language for Verification
- Verilog Language Fundamentals
- Verilog Language and Application
- Verilog for Design Synthesis
- Verilog for Verification
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PCB Design
- Advanced Design Verification with the RAVEL Programming Language
- Allegro Design Entry HDL Basics
- Allegro Design Entry HDL Front-to-Back Flow
- Allegro Design Entry HDL SKILL Programming Language
- Allegro Design Entry Using OrCAD Capture
- Allegro Design Entry Using OrCAD Capture
- Allegro Design Reuse
- Allegro EDM Administration for OrCAD
- Allegro EDM PCB Librarian
- Allegro EDM for Administrators
- Allegro EDM for Engineers and Designers
- Allegro FPGA System Planner
- Allegro High-Speed Constraint Management
- Allegro PCB Editor Advanced Methodologies
- Allegro PCB Editor Basic Techniques
- Allegro PCB Editor Intermediate Techniques
- Allegro PCB Editor SKILL Programming Language
- Allegro PCB Librarian
- Allegro PCB Router Basics
- Allegro RF PCB
- Allegro Sigrity PI
- Allegro Sigrity SI Foundations
- Allegro System Architect
- Allegro Team Design Authoring
- Allegro Tool Setup and Configuration
- Allegro Update Training
- Analog Simulation with PSpice
- Analog Simulation with PSpice Advanced Analysis
- Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
- OrCAD Capture Constraint Manager PCB Flow
- Sigrity 1. Power Integrity Analysis - From DC to AC
- Sigrity 1. Power Integrity Analysis - From DC to AC
- Sigrity 2. Power Aware Signal Integrity Analysis Part-I: For DDRx Analysis
- Sigrity 2. Power Aware Signal Integrity Analysis Part-I: For DDRx Analysis
- Sigrity 3. Power Aware Signal Integrity Analysis Part-II: For Serdes Analysis
- Sigrity 3. Power Aware Signal Integrity Analysis Part-II: For Serdes Analysis
- Sigrity PowerDC and OptimizePI
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
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System Design and Verification
- C++ Language Fundamentals for Design and Verification
- Comprehensive RTL Signoff by Designers Using JasperGold Superlint
- Creating Assertions for SV Real-number Modeling (Webinar)
- Essential SystemVerilog for UVM
- Foundations of Metric Driven Verification
- Incisive SystemC, VHDL, and Verilog Simulation
- Indago Debug Analyzer App
- JasperGold Formal Expert
- Low-Power Simulation with CPF
- Low-Power Simulation with IEEE Std 1801 UPF
- Perspec System Verifier – Basic
- SVA, Formal and JasperGold® Fundamentals for Designers
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Assertions
- SystemVerilog Language for Verification
- Verilog Language Fundamentals
- Verilog Language and Application
- Verilog for Design Synthesis
- Verilog for Verification
- Xcelium Simulator
SELF PACED ONLINE TRAINING
Online Training Subscription
Multiple online courses of one or more technology groups, for 12 months unlimited, per student
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus