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All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Cadence Online Collection Subscriptions
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Custom IC / Analog / RF Design
Circuit Design and Simulation- Design Checks and Asserts
- Physical Verification System
- Spectre Simulator Fundamentals S1: Spectre Basics
- Virtuoso ADE Assembler S1: Introducing the Assembler Environment
- Virtuoso ADE Assembler S2: Sweeping Variables, Simulating Corners, and Creating Run Plans
- Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator
- Virtuoso ADE Explorer S2: Analyzing Simulations Using the Virtuoso XL Waveform Tool
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Analog Design Environment
- Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
- Virtuoso Schematic Editor
- Virtuoso System Design Platform
- Virtuoso Visualization and Analysis XL
Circuit Simulation- Design Checks and Asserts
- Spectre Accelerated Parallel Simulator
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Virtuoso AMS Designer
- Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
- Virtuoso Spectre RF
Layout Verification- Assura DRC/LVS Rules Writer
- Assura Verification v3.1.7 (Classroom)
- Cadence QRC RF Transistor and Substrate-level Extraction
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
Physical Design- SKILL Language Programming Introduction
- Using Virtuoso Constraints Effectively
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T2 Create and Edit Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T5 Interactive Routing (XL)
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Space-Based Router Express
- Virtuoso Space-based Router
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Digital Design and Signoff
Silicon Signoff- Basic Static Timing Analysis
- Cadence QRC RF Transistor and Substrate-level Extraction
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
Synthesis and Test- Advanced Synthesis with Genus Stylus Common UI
- Advanced Synthesis with Genus Synthesis Solution
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Genus Synthesis Solution with Stylus Common UI
- Joules™ Power Calculator
- Low-Power Synthesis Flow with Genus Synthesis Solution (Libraries not included)
- Test Synthesis Using Genus Synthesis Solution
- Test Synthesis with Genus Stylus Common UI
- Virtuoso Digital Implementation
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IC Package Design and Analysis
SI/PI Analysis Integrated Solution- Allegro Sigrity PI
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity SI Foundations
- Sigrity 1. Power Integrity Analysis - From DC to AC
- Sigrity 2. Power Aware Signal Integrity Analysis Part-I: For DDRx Analysis
- Sigrity 3. Power Aware Signal Integrity Analysis Part-II: For Serdes Analysis
- Sigrity PowerDC and OptimizePI
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Languages and Methodologies
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PCB Design and Analysis
PCB Layout- Advanced Design Verification with the RAVEL Programming Language
- Allegro Design Entry Using OrCAD Capture
- Allegro High-Speed Constraint Management
- Allegro PCB Editor Advanced Methodologies
- Allegro PCB Editor Basic Techniques
- Allegro PCB Editor Intermediate Techniques
- Allegro PCB Editor SKILL Programming Language
- Allegro PCB Router Basics
- Allegro RF PCB
- Allegro Tool Setup and Configuration
- Allegro Update Training
SI/PI Analysis Integrated Solution- Allegro PCB SI Foundations
- Allegro Sigrity PI
- Allegro Sigrity SI Foundations
- Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
- Sigrity 1. Power Integrity Analysis - From DC to AC
- Sigrity 2. Power Aware Signal Integrity Analysis Part-I: For DDRx Analysis
- Sigrity 3. Power Aware Signal Integrity Analysis Part-II: For Serdes Analysis
- Sigrity PowerDC and OptimizePI
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System Design and Verification
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Tensilica Processor IP
INSTRUCTIONAL VIDEOS
Training Bytes
Log into Cadence Online Support to watch our short videos to explore an element of a language, make sense of a methodology, or learn how to do a task
SELF PACED ONLINE TRAINING
Online Training Subscription
Multiple online courses of one or more technology groups, for 12 months unlimited, per student