Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Shorten simulation run time with optimized C-core VIP supporting all simulators, languages, and methodologies
- Easy test writing with consistent and open UVM API and built-in coverage model, sequences, and error injection
- No silicon escapes with the most accurate and comprehensive protocol and timing checks
- Out-of-the-box comprehensive compliance verification suite for the latest protocols with TripleCheck™
The Cadence® Verification IP (VIP) Catalog and memory models are optimized for the IP, SoC, and system-level testing required for today's designs. All Cadence VIP come with Pureview automated configuration and TripleCheck™ IP Validator compliance suite for complete verification coverage of your IP within the SoC. Cadence VIP runs seamlessly on our Xcelium™ simulator, Palladium™ Z1 emulation platforms, and any third-party simulator to speed up the verification process.
The Cadence VIP portfolio supports customers developing SoCs for automotive, hyperscale data center, and mobile applications.
Cadence VIP Portfolio – One Stop Shop for all protocols and memories
See What Customers Have to Say About Cadence VIP
Click through to the next section for customer presentations.
- NVMe Advanced Verification, Broadcom, CDNLive India 2019
- Verification of GDDR6 High-Speed Memory PHY IP Using Cadence VIP, Rambus, CDNLive India 2019
- Experiences with Deploying Cadence's PCIe VIP Solution in UVM-Based PCIe Controller Testbench, Nvidia, CDNLive India 2017
- SoC Interconnect Verification Using Verification Workbench and IP-XACT Flow, Samsung, CDNLive India 2017
- DisplayPort IP Verification Challenges and Solutions for Ultra High Resolutions (4K) and MST, Samsung, CDNLive India 2017
- Streamline the Verification Flow and Apply to DisplayPort 8K4K Design, Samsung Semiconductor, CDNLive India 2017
Cadence’s development of verification solutions for USB4 is a key step forward for the development of compliant designs and ensuring the continued growth of the Thunderbolt ecosystem based on USB open standards.
Jason Ziller, general manager of Client Connectivity Division at Intel
Broadcom has been a leader in the Bluetooth market for more than 15 years, and we continue to invest in mobile wireless technology to grow our market position. With Cadence VIP for Bluetooth 5, engineers can focus on designing complex SoCs and delivering more value to end customers.
Michael Hurlston, senior vice president and general manager at Broadcom
When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP...we rely on Cadence's high-quality, interoperable design and verification IP solutions, and excellent customer support to meet the PCIe 2.0 and IOV specifications...
Jim Finnegan, senior vice president of Silicon Engineering at Netronome
Cadence PCIe 3.0 Verification IP has enabled us to thoroughly verify that our designs comply with the PCIe 3.0 specification and the new PCIe 4.0 product demonstrates the company’s commitment to supporting engineers working with this key protocol.
Balaji Kanigicherla, founder, CTO and vice president of Engineering at Ineda Systems
The Cadence solution for PCIe 5.0 is important to our development of the next generation of our products, to support the need for faster data speeds for high-performance, machine learning, cloud, storage and more applications.
Shlomit Weiss, senior vice president, silicon engineering at Mellanox Technologies
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview