Best-in-class USB Verification IP for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides a mature and comprehensive verification IP (VIP) for the USB protocol, which is part of the USB family. Incorporating the latest protocol updates, the USB VIP is not only a complete bus functional model (BFM) for the DUT but it also provides integrated automatic protocol checks and coverage model. USB VIP is designed to make it easy for you to integrate in testbenches for IP, system-on-chip (SOC), and system level. The USB VIP helps you to reduce time to test by accelerating verification closure and ensuring end product quality.

The VIP for USB runs on all major simulators and supports all main verification languages, such as Verilog, System Verilog, and e, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specifications: USB3.2, USB 3.1, USB3.0, USB2, USB1.1 and xHCI.

USB diagram 1
USB diagram 2
USB diagram 3

Product Highlights

  • Support for testbench languages such as SystemVerilog, UVM, OVM, and e
  • Runs on all major simulators such as Xcelium, VCS, or MTI
  • Generation of constraint-random bus traffic
  • Dynamic activation and reconfigure the VIP attributes anytime during the simulation
  • Register interface flow to change timing parameters to reduce simulation time
  • Built-in verification plan, protocol checks, and coverage model
  • Callback access at multiple TX and RX queue points for Scoreboarding, collect data coverage, and data manipulation
  • Support for trace debug capability, packet tracker, and waveform debugger

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name



  • Gen2x2, Gen1x2, Gen2x1, and Gen1x1

Supported DUT Models

  • Host, Device and PHY Model for USB2 or USB3
  • Hub Model (3.2/3.1/3.0/2.0)
  • xHCI Model (Extensible Host Controller Interface)
  • Re-timer Model
  • Re-driver Model

Supported Interfaces

  • Serial (TX/TX_, RX/RX_)
  • DPDM (Dp/Dm)
  • HSIC
  • UTMI/UTMI+ (MAC or MACRO (include-PHY) with 8 or 16-bit data width)
  • PIPE (MAC, PHY, or MACRO (include-PHY) with 8, 16, or 32-bit PIPE width)

OTG Support

  • OTG 1.3, 2.0, and 3.0 revisions with both A-device and B-device configurations

OTG Protocol

  • SRP, ADP, HNP and RSP

Framework and Protocol Layer

  • Control, Bulk, Isochronous, Interrupt Transfers
  • SSI (Smart Isochronous)
  • Bulk Streaming
  • Data Bursting
  • Updates value of Endpoint Companion and Isochronous Endpoint Companion descriptor type

Physical Layer

  • 8b/10b (Gen1x2) and 128b/132b (Gen2x2) encoding/decoding per lane
  • Separate clock source per lane
  • Spread Spectrum Clocking (SSC)
  • Control for SKP and SYNC insertion
  • Clock Recovery
  • Lane-Lane De-skew on Rx
  • LFSR per lane and enable/disable scrambling
  • PHY loop-back state with bit error rate test
  • Re-timer presence announcement based on LBPM signaling 
  • Fe-timer SKP number calculation in Host and Device VIP

Link Layer

  • Link Power Management U0, U1, U2, and U3
  • RTSSM and LTSSM with user control to direct into any state
  • Nullified and partially nullified DP
  • Loopback and Compliance
  • Ux Exit on configuration lane
  • Speed negotiation and fallback for host, device, hub
  • ByPass Link training
  • Holding VIP LTSSM until DUT is ready

Extensible Host Controller Interface

  • Support for user control to initialize MMIO and host memory space
  • Additional hooks in the TB to connect xHCI driver with PCIE interface
  • TRBs (Multi/Single), Command TRB, Event TRB, Transfer TRB, other TRB
  • Scatter-Gather Transfers
  • Scratchpad buffer
  • Command Interface/Ring (Command Ring, Event Ring, Transfer Rung)/Input Context and Device Context
  • Supports all types of transactions

Protocol Traffic

  • Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions
  • Full control on the device VIP to do flow control, such as sending NRDY or ERDY

Loopback and BERT

  • PHY loop-back state with bit error rate test


  • Hub training, basic topology enumeration, packet routing, and forwarding
  • USB3.1/3.2 Hub with manual enumeration, basic topologies, training, packet forwarding


  • Bypass the enumeration process and do backdoor register writing for set_address and set_config
  • Manual enumeration
  • Enable auto enumeration process from the host VIP

Register Interface

  • Change the severity (Error, Warning, Info) of protocol assertions
  • Initiate low-power enter/exit sequences from the VIP
  • Control functionality such as end-point buffers, to exercise device flow control, streaming
  • Collect VIP model information, such as device states, device address, end-point information, LTSSM states, and more. The information can easily accessed in the testbench

Error Injection

  • Predefined error injections such as Crc5, Crc16, and Crc32 for header packets, link commands, data packets, discarding a packet
  • Additional Error Injection scenarios can be generated using VIP callbacks

Tunneling with USB4

  • Support for USB4 Interface (USB3 Tunneling)

Simulation Test Suite

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing.

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