Gold standard for PLB device for your IP, SoC and system-level design verification.

In production since 2011.

This Cadence® Verification IP (VIP) supports the IBM PLB standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for PLB is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. The PLB VIP supports DCR, PLB4, and PLB6, for core, devices, and bus controller.

Supported specification: PLB4 and PLB6 Specifications - IBM confidential.

PLB diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Transaction and memory callbacks for all protocol, model states, and device events
  • Error injection capability including error injection types for Read/Write data parity and address parity errors
  • Ability to dynamically change configuration parameters
  • Extensive functional coverage in SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name



  • Command, read data, and write data buses - DCR, PLB4, PLB6


  • Core, device, snooper pin, and snoopable and non-snoopable commands - PLB4, PLB6

Address ordering

  • Address overlapping read/write - PLB4, PLB6

Cache coherency

  • Cache coherency for snoopers - PLB6

Data transfer

  • Supports bytes, half-word, word, or line/burst transfer - PLB4, PLB6

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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