JTAG Verification IP for your IP, SoC, and system-level design testing.

The Cadence® JTAG Verification IP provides support for the JTAG protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. JTAG VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

JTAG standard defines test logic that can be included in an integrated circuit to provide standardized approaches to:

  • Testing the interconnections between integrated circuits once they have been assembled onto a circuit board or other substrate.
  • Testing the integrated circuit itself.
  • Observing or modifying circuit activity during the component's normal operation.

The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).

Supported Specification: JTAG Specification IEEE Std 1149.1-2013.

JTAG diagram

Product Highlights

  • Constrained-random traffic generation for both manager and subordinate
  • Comprehensive checkers for specification compliance.
  • Coverage: Monitors, checks, and collects coverage on bus traffic
  • Error injection support
  • Transaction tracker: Configurable tracking of all the transactions

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


Multiple subordinates

  • Supports multiple subordinates. Parallel/serial configuration is supported


  • Supports all standard defined instructions


  • Optional instruction CLAMP is supported

High Z

  • Optional instruction HIGHZ is supported


  • Optional instruction EXTEST is supported

Extest Pulse

  • Optional instruction EXTEST_PULSE is supported (from 1149.6 standard)

Extest Train

  • Optional instruction EXTEST_TRAIN is supported (from 1149.6 standard)

Instruction Length

  • Instruction length is configurable

Instruction Codes

  • Instruction codes are configurable

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

Master your tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with Online trainings, VIP Portal, application notes, and troubleshooting articles