I2C Verification IP for your IP, SoC, and system-level design testing.

The Cadence I2C VIP provides support for the I2C protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. I2C VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in Fast-mode, up to 1 Mbit/s in Fast-mode Plus (Fm+), or up to 3.4 Mbit/s in High-speed mode. The Ultra Fast-mode is a uni-directional mode with data transfers of up to 5 Mbit/s. The VIP meets requirements of both higher bus speeds and lower supply voltages. The VIP facilitates development of true multi-master environments with large numbers of peripherals.

Supported specification: I2C Protocol Specifications v1.0, v2.0, v2.1, v3.0, and v5.0.

I2C diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Contains predefined checks to verify that the DUT agents, controller and target, adhere to the protocol rules
  • Generates I3C traffic as controller, target, or multi-agent driving with the ability for constrained-random bus traffic
  • Provides ability to generate intentionally erroneous traffic on the bus
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Provides extensive coverage in SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


Multiple Agents

  • Multi-controllers and any number of targets


  • Controller arbitration is supported

Clock Stretching

  • Stretching of the SCL clock

7-bit/10-bit Addressing

  • Configurable option to use for slave addressing

General Call

  • Optional command support, configurable for each slave

Start Byte

  • Sending of optional start byte in transactions is available

Speed Modes

  • All speed modes are supported: Standard, Fast, Fast Plus, High Speed, and Ultra Fast

Glitch Handling

  • Supports optional glitch handling

Slave Response Control

  • Implements user control of slave response fields such as data, slave busy, slave sending NACK, etc.

Software Reset

  • Optional software reset command is supported

Device ID

  • Optional command Device ID is supported

Simulation Test Suite

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing.

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