Best in class MIPI® SoundWiresm Verification IP for your IP, SoC, and system-level design testing.

In production since 2015 on dozens of production designs.

The Cadence®Verification IP (VIP) for the MIPI® SoundWiresm Protocol provides a bus functional model (BFM), integrated automatic protocol checks and coverage model. It supports active or passive Manager, monitor, and a configurable number of Peripherals (1-11).

The VIP for SoundWire runs on Cadence Incisive® Enterprise Simulator, as well as third-party simulators, and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

Supported Specifications: MIPI SoundWire specifications v1.0, v1.1, and v1.2.

MIPI Soundwire diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging of frames and data payload
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in e and SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


Multi-lane Payload Transport

  • Up to 8 data lanes are supported

High-PHY Mode

  • High-performance PHY


  • Sync Peripheral with Manager SoundWire frame


  • Manager assigns Dev_num for each newly attached Peripheral

Data Payload Traffic

  • Peripheral and Manager devices can send data payload traffic

Bank Switching

  • Frame size and DP channels can be switched during activity


  • Ability to perform all kinds of resets on the fly

Error Scenarios

  • Manager and Peripheral can generate error scenarios


  • Peripheral VIP replies automatically when interrupt needs to be generated based on configuration

Dynamic Peripheral Devices

  • Dynamic addition and removal of Peripheral devices

Multicast and Broadcast Peripheral Accesses

  • Manager can access Peripheral registers through broadcast and multicast

Test Data Modes

  • Support of static and PRBS data payload sending

Peripheral Command Responses

  • Peripheral VIP automatically replies with appropriate command responses

Command Ownership

  • Monitor can take command ownership from Manager

Flow Control

  • Peripheral and Manager devices can send asynchronous data payload traffic

Bulk Payload

  • Peripheral and Manager devices support Bulk Payload Transport Protocol

Manager PHY Test mMdes

  • Manager device supports PHY test modes

Full, reduced, and simplified data ports

  • Support in Full, Reduced, and Simplified Data Ports

Limited WordLength

  • Support in a limited set of values of the WordLength field

SDCA Interrupt Handling

  • Support all the SDCA interrupt registers and interrupt cascading

Severe Reset

  • Support to handle severe reset condition added

PHY Controlling Registers

  • Added support for PHY controlling registers

Simulation Test Suite

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing.

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