Best-in-class DisplayPort® Verification IP for your IP, SoC, and system-level design testing.
Used by market leaders driving the specification.
The Cadence® Verification IP (VIP) for DisplayPort is the industry's most comprehensive protocol validation solution for DisplayPort designs. It provides a complete bus functional model (BFM) and protocol monitor with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort VIP is designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.
The VIP for DisplayPort can be used as standalone, as a platform for running TripleCheck tests, and/or enabling DSC VIP on top of the base VIP. The VIP for DisplayPort is compatible with all main verification languages such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera, methodologies such as UVM, OVM, and VMM, and runs on all leading simulators.
Supported specifications: VESA DisplayPort versions 1.2a, 1.3, 1.4, 1.4a, 2.0, and 2.1 and Embedded DisplayPort (eDP) versions 1.3, 1.4a, 1.4b, and 1.5.
Testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
Powerful error injection capability with predefined errors or through callbacks
Enables bypass of training mode to link devices
Generates constrained-random bus traffic over all channels: Main Link, AUX, and HPD
Display Stream Compression (DSC) support
Provides extensive coverage in e and SystemVerilog
The following table describes key features from the specifications that are implemented in the VIP:
Source, Sink, Link Training-Tunable PHY Repeater (LTTPR/retimer)