- Verifies compliance to standard protocols with exhaustive assertion-based verification IP libraries
- Enables automated, encapsulated, plug-and-play capabilities
- Provides quality support for spec-compliant designs
Optimized for high-performance execution and rapid debug, Cadence® Assertion-Based Verification IP (VIP) consist of libraries of assertion-based VIP for exhaustively verifying the compliance of a design under test (DUT) to a given protocol. With our Assertion-Based VIP, you can find critical bugs early on and shorten your overall verification schedule.
All of our Assertion-Based VIP are optimized for high-performance execution in our formal engines and JasperGold ProofGrid™ Intelligent Resource Manager, along with rapid debug with our unique JasperGold QuietTrace™ debugging capability. The VIP also work with our unique JasperGold Visualize™ Interactive Debug Environment for early integration of your implementation and the kit and/or rapid protocol customization/extension. The Assertion-Based VIP include reusable “recipes” to explore protocol functionality and intent based on interface events. The protocol-related properties generated support early exploration and verification of protocol specifications, are optimized for formal, and plug seamlessly into the simulation environment.
In the case of Arm® protocols, all of Cadence’s Arm-related Assertion-Based VIP products are Arm certified and optimized for high performance with our formal engines and debug workflow. Each VIP offering works with our JasperGold® Formal Property Verification (FPV) App to formally prove the embedded properties. As a result, you won’t need to manually write properties. The Assertion-Based VIP also work with many other JasperGold Apps. When an Assertion-Based VIP is used with these apps, you can visualize protocol transactions and timing diagrams to understand behaviors of properties as well as design specifications via our Visualize technology.
- Using the Assertion-Based VIP with the JasperGold FPV App eases debugging thanks to powerful Visualize technology that displays “live” interesting waveforms. If a counterexample is found, constraints can be added or modified on the fly using Visualize technology.
- QuietTrace technology simplifies the debug process even further, calculating the minimum signal activity needed to describe the behavior in question. This greatly accelerates your exploration and debugging tasks.
- Assertion-Based VIP products are easy to adjust to support cases where you are tailoring and/or only implementing a subset of a given protocol
- All Assertion-Based VIP products include reusable “recipes” to explore protocol functionality and intent based on interface events
- The Assertion-Based VIP properties are written in standard IEEE SystemVerilog Assertions (SVA) and are optimized for runtime and memory performance with our formal engines
- Cadence Assertion-Based VIP are available for the following protocols:
Available Assertion-based VIP:
- Arm AMBA® AHB
- Arm AMBA AHB-Lite
- Arm AMBA APB
- Arm AMBA ATB
- Arm AMBA 3 AXI
- Arm AMBA 4 AXI
- Arm AMBA 4 AXI-Lite
- Arm AMBA 4 AXI-Stream
- Arm AMBA AXI ACE
- Arm AMBA AHB5
- Arm AMBA AXI5
- Arm AMBA5 CHI