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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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客製IC/類比/RF設計

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系統設計與驗證

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC封裝設計與分析

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嵌入式軟體

PCB設計與分析

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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ZH - Taiwan
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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
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        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
  • 支援與培訓
      • Support
        • Support Process
        • Online Support
        • Software Downloads
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        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
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Formal and Static Verification
  • Key Benefits
  • Portfolio of Products
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  • Key Benefits
  • Portfolio of Products
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  • Related Products

Jasper Formal Verification Platform

Smart formal verification apps developed for C/C++ and
RTL level verification to find and fix bugs early in the
design cycle

overview

Find More Bugs in Less Time, Earlier in the Design Process

The Cadence® Jasper™ Formal Verification Platform consists of formal verification apps at the C/C++ and RTL level. They use smart proof technology and machine learning to find and fix bugs and improve verification productivity early in the design cycle.

double-blocks

Key Benefits

Productivity

Increases verification throughput and eases debug

Efficiency

Efficiency: Inherently exhaustive—finds corner-case bugs often missed by simulation

Accuracy

Signoff-accurate formal coverage fully integrated with Cadence’s vManager™ Verification Management

Portfolio of Products

The Jasper Formal Verification Platform consists of formal verification apps that can be used at every stage of the design cycle.

Jasper C Apps

Our Jasper C/C++ Apps can be used for applications that are algorithm-centric and datapath-heavy such as artificial intelligence and machine learning (AI/ML), graphics, image processing, and encryption.

Learn More

Jasper RTL Apps

Our suite of Jasper RTL Apps can be used when the design compilation process sets the maximum size of design, and the compute resources necessary, to start formal analysis.

Learn More

Resources

Announcing Jasper C2RTL App: Formal for Algorithmic Designs
Learn More
Cadence Collaborates with the University of Oxford to Develop the New Jasper C2RTL App
Watch Now

Related Products

vManager Verification Management

A powerful, scalable, and automated verification planning and management solution from spec to execution to signoff

Learn More

Xcelium Logic Simulation

Provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC, e, UVM, mixed-signal, low power, safety and X-propagation

Learn More

Palladium Emulation

Comprehensive support for multiple use cases enabling early software development, hardware/software debug, and real-world testing

Learn More

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