Best Verification Throughput for Pre-Silicon Verification and Debug
Cadence® Palladium® emulation platforms provides early software development, hardware/software verification and debug, and in circuit emulation. It provides the highest debug productivity early in the design cycle when the RTL is still changing.
Palladium Z2 Enterprise Emulation Platform
Our newest emulation platform delivers increased verification performance and capacity over previous emulation platforms. The Palladium Z2 emulation platform scales from job sizes as small as 8M gates to as large as 18.4B gates and dramatically accelerates compile times with a revolutionary new modular compiler.
Palladium Z1 Enterprise Emulation Platform
Our first-generation enterprise emulation system bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation.
Complementing our emulation systems is our industry-leading, most comprehensive portfolio of physical and virtual interfaces to make using Palladium platforms even easier and more productive.
The Palladium Z2 platform offers enhancements above and beyond emulation systems:
Verified with Cadence
Learn how our customers use the Dynamic Duo to optimize workload distribution between verification, validation and pre-silicon software bring-up and adopt a shift-left methodology to accelerate their product development process.
AMD Designs 3rd-Gen EPYC Server Processors for HPC with Dynamic Duo
Palladium and Protium help AMD push emulation in capacity, next-gen testbench design, advanced clocking, and hybrid use.
With twice the useable capacity, 50 percent higher throughput, and faster modular compiler turnaround, we can validate our most sophisticated GPU and SoC designs comprehensively and on schedule.
Narendra Konda, Senior Director, Hardware Engineering, NVIDIA Corporation
The ability to perform design bring-up and transition between the Palladium Z2 emulation and the Protium X2 prototyping platforms in short time provides us with the opportunity to optimize our shift-left deployment for our most challenging SoC designs.
Alex Starr, Corporate Fellow, Methodology Architect, AMD
Best-in-class emulations are key to our success, and Arm uses emulation extensively together with simulation on Arm-based servers to achieve the highest verification throughput.
Tran Nguyen, senior director of Design Services, Arm