Verification Throughput for Pre-Silicon Verification and Debug

With Cadence® Palladium® emulation platforms, design and verification teams have comprehensive support for multiple emulation use cases with the highest debug productivity early in the design cycle when the RTL is still changing.

Palladium Z2 Enterprise Emulation Platform

Our newest enterprise emulation platform delivers increased capacity and performance over previous platforms. The Palladium Z2 platform scales from job sizes as small as 8M gates to as large as 18.4B gates and dramatically accelerates compile times with a revolutionary new modular compiler.

  • 2X capacity, 1.5X performance over Palladium Z1 platform
  • Modular compile for faster turnaround time: 10 billion gates in less than 10 hours
  • 10X faster waveform dump and 2X debug trace depth, 2X faster memory dump and debug upload, and 3X throughput bandwidth to the host
  • FullVision 2.0—new and improved high-performance debug engine
  • Scalability from 8 million gates to 18.4 billion gates

Palladium Z1 Enterprise Emulation Platform

Our first-generation enterprise emulation system bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation.

  • Scalable capacity up to 7 billion gates
  • Compiles up to 140 million gates per hour
  • Workload allocation and capable of job reshaping
  • Superior debug depth and upload speeds

Interface Support

Complementing our emulation systems is our industry-leading, most comprehensive portfolio of physical and virtual interfaces to make using Palladium platforms even easier and more productive.

  • SpeedBridge® Adapters: Protocol interface solutions that enable efficient driver and application-level testing with Palladium emulation and Protium prototyping systems
  • EDK: Pre-validated, off-the-shelf, data center-ready emulation server with a SpeedBridge adapter pre-installed
  • Memory models: Comprehensive portfolio supports most industry-standard memory models
  • VirtualBridge™ Adapters: Enable user applications and OS drivers to establish a virtual protocol connection to Palladium emulation and Protium prototyping systems
  • Accelerated VIP: A comprehensive set of high-performance protocol IP to verify the interfaces and peripherals of your SoC

Use Models

The Palladium Z2 platform offers enhancements above and beyond emulation systems:

  • Code and functional coverage dump 
  • Hardware verification language-based testbench acceleration
  • In-circuit emulation 
  • In-circuit acceleration 
  • Hybrid acceleration with virtual platform
  • Universal Verification Methodology (UVM) acceleration
  • Vector-based acceleration 
  • Multi-power domain verification with IEEE 1801 UPF constraints
  • Hardware-based and post-process-based massively parallel Dynamic Power Analysis (DPA)

Verified with Cadence

Learn how our customers use the Dynamic Duo to optimize workload distribution between verification, validation and pre-silicon software bring-up and adopt a shift-left methodology to accelerate their product development process.