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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
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        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
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Palladium Hybrid

Delivers a 60X speed-up of OS boot over in-circuit emulation for pre-silicon software validation

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Key Benefits

  • High-performance software execution: Effective software execution speeds exceeding those of standalone emulation and, for certain use cases, outperforming FPGA prototypes
  • Early software validation: Can be applied soon after enough RTL is available, enabling an early start to software and SoC validation processes
  • Increased validation throughput: This results from combining early validation start, shorter software-driven test runtime, better hardware/software debug, and increased number of concurrent users per emulator
  • Accelerated embedded software development: ARM and Cadence have partnered to accelerate embedded software development earlier in the design cycle

The Cadence® Palladium® Hybrid solution integrates a high-performance transaction-level model of the CPU subsystem running on Cadence Virtual System Platform (VSP) with register-transfer level (RTL) for the rest of the SoC running on the Palladium platform. The solution accomplishes this by using Cadence’s exclusive Software Integrator technology to provide cross-domain memory coherency. This solution enables the software to execute at virtual platform speeds (typically between 50 – 100MIPS) and interact with the RTL of the design. The Palladium Hybrid tool also maintains memory coherency between the RTL and virtual domains, delivering 60X improvement in operating system (OS) boot and 10X improvement in post-boot software execution. 

With the Palladium Hybrid solution, you can start software validation up to six months earlier in the design cycle as a result of the fast compile and turnaround times the platform offers. This can typically give you a six-month head start on software validation, which can begin prior to the RTL code freeze where typical FPGA prototyping usually starts. 

Accelerating Embedded Software Development Earlier in Design Cycle

ARM and Cadence have teamed up to accelerate embedded software development earlier in the design cycle. Using Palladium Hybrid technology and ARM® Fast Models, ARM achieved a 50X faster OS boot-up during the development of its ARM Mali™-T760 GPU.

Compared to the previous emulation-only solution, the combination of Palladium Hybrid technology and ARM Fast Models resulted in an up to 10X speed-up of overall hardware-software testing, reducing ARM’s time from OS boot-up to test from hours to minutes while also improving turnaround time and system quality. This development speed gain boosts the ARM Mali Midgard architecture into a new era of energy efficiency.

Palladium Hybrid Example
Palladium Hybrid Example

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Co-develop and Co-verify Pre-Silicon Hardware Designs Using Palladium Hybrid Solution

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NVIDIA - Palladium/VSP ARM v8 Tegra Hybrid

Using Palladium/VSP Hybrid to Accelerate SW Development

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  • Cadence 推出Helium Virtual和Hybrid Studio 加速了行動設備、汽車和超大規模系統的開發 09/22/2021

  • EdgeCortix Collaborates with Cadence to Accelerate AI Chip Design 06/02/2021

  • Cadence Collaboration with Arm Enables Customers to Successfully Tape out Next-Generation Arm Mobile Designs 05/25/2021

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