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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
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          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
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          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
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Allegro PCB DesignTrue DFM Technology

Real-time DFM checks ensure manufacturability

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Key Benefits

  • Reduce rework and shorten cycles by running manufacturing DRC in-design, while designing
  • Wide range of spacing and copper area requirement rules to ensure manufacturability, fabrication, and assembly, independent of electrical requirements
  • Easy to configure, apply contextually, and reuse manufacturing rules
  • Work directly with a participating manufacturer in the DesignTrue DFM Program portal to download DFM rules before you design

Manufacturability Comes First

What wouldn’t you do for manufacturability? Your entire design team drops everything they’re doing to go back and make changes to a design you thought was already done. You put all your future projects in jeopardy to save a past project. Because if you don't, there may not be any future projects. This nightmare scenario is all too familiar even though we know this isn’t sustainable. We need to find those errors earlier.

Cadence® Allegro® PCB DesignTrue DFM Technology lets you actually design for manufacturability—not redesign for manufacturability, not make frequent changes for manufacturability—and accelerate new product introduction. Define your manufacturer’s rules before you start, and apply them in real time as you design. That way, when you’re finished with the design, you’re already all ready for first-pass DFM signoff.

Real-Time Manufacturability Rule Checks While Designing

The best time to run design for manufacturing (DFM) checks? The past. The second best? Now. In-design DesignTrue DFM checks in the Allegro PCB Editor are always running as you design. You'll have already run all your design rule checks before you go to final signoff. When you do, signoff is smoother with less to fix, and less stressful when your release schedule is unharmed. All while keeping manufacturability above all else.

Broad Set of Rules for All Manufacturability Constraints

The signoff process is probably the most nerve-racking experience for engineers and managers. DFM signoff is no different. The DesignTrue DFM technology in the Allegro PCB Editor provides a wide set of checks to ensure the manufacturability of your designs. Spacing between copper features such as traces, pins, vias, and solder joints relative to the board outline and other copper features can be verified in real time while you design, independent of electrical and signal-based rules. But manufacturability is more than just copper spacing; it’s volume, and non-copper features, like holes and silkscreen printing, which all come into play at fabrication and assembly times. With over 2,000 checks, engineers and managers can be confident that their designs are electrically sound and manufacturable, too.

Easy to Use, Reuse, and Apply, Selectively, Exclusively, and Globally

Manufacturability rules are easy to manage and collaborate on. Just like electrical constraints, the easy-to-use spreadsheet interface is intuitive for engineers and non-engineers alike, which makes re-use easy. The constraints are highly configurable with the ability to enable and disable groups and whole categories of rules, or individual rules. Rules can be applied in etch mode, non-etch mode, and in stack-up mode, giving designers the ability to isolate layers, geometries, and cutouts.

DesignTrue DFM Partner Program

Join the DesignTrue DFM Partner Program where you can receive the technology files you need from participating manufacturing partners to ensure PCB design manufacturability early in the design process, reducing rework and shortening design cycles. You then use Allegro PCB DesignTrue DFM technology to integrate the rules as you design to reach signoff faster. Access the DesignTrue DFM Partner Program portal. 

Contact Us

DesignTrue DFM Partner Program
ENTER PORTAL
Preventing DFM Errors with Proven Design Principles
READ ARTICLE

See how real-time DFM check violations are shown in the PCB design canvas to let you find and fix errors now, not later.

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Real-Time DFM Verification

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  • Cadence發布新一代Sigrity X打造10倍快的系統分析 03/16/2021

  • Rockley Photonics Collaborates with Cadence to Create a High-Performance System for Hyperscale Data Centers 12/02/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

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