Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces
Cadence expanded its Sigrity™ technology portfolio with new products and capabilities:
- Upgraded serial link analysis flow to accelerate the time to pass compliance tests
- New IBIS-AMI model building technology takes industry-proven equalization algorithms and provides a wizard-based graphical interface to rapidly facilitate creation of IBIS-AMI models. Available in two tiers, one that enables creation of models strictly for Sigrity tools, and another that creates models suitable for any IBIS-AMI compliant simulator.
- New cut-and-stitch model extraction technology allows for segmenting long serial links into sections that should be modeled using 3D full-wave and sections that can be modeled using hybrid extraction technology. The resultant model is extracted 10X faster than a strictly 3D full-wave extraction with 95% accuracy.
- New USB 3.1 (Gen 2) compliance kit to confirm that the 10Gbps interface requirements are met.
- Optimized design flow between PCB designer and power integrity engineer
- New cross-probing between DC analysis report file and Allegro® editing canvas
- Batch DC analysis available directly from the Allegro editing canvas
- Review previously generated DC analysis report files from the Allegro editing canvas
- Optimized design flow between IC package designer and characterization engineer
- Batch electrical performance assessment (EPA) available directly from the IC package designer’s editing canvas
- Batch package model creation using hybrid solver technology directly from the IC package designer’s editing canvas
- Review previously generated EPA report data from the IC package designer’s editing canvas
- Sigrity XtractIM™ technology
- Upgraded 3D interconnect modeling to enable rapid modeling of low-cost PCB and IC packages
- New rapid and accurate capacitance extraction technology
- Quickly produce RLCG interconnect models for designs with few (or no) power and ground planes/shapes using new 3D quasi-static extraction technology
DesignCon 2016: Sigrity 2016 Portfolio Highlights
Ken Willis, Cadence product engineering director, discusses the company's DesignCon 2016 highlights ranging from serial link analysis and DDR/LPDDR support to the Sigrity 2016 portfolio's new products and enhancements including generating AMI models and a quasi-static field solver.