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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
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What's New in Sigrity

New products, updated features, and purchasing options

  • What's New in Sigrity
  • Sigrity 2017
  • Sigrity 2016
  • Sigrity 2015

Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis

Interconnect Modeling Technology

Upgraded interconnect modeling technology addresses latest trends on PCB and IC package design.With signal speeds climbing to 32Gbps and faster, the need to strategically model PCBs and connectors as one structure is now required. The new Cadence® Sigrity™ 3D Workbench, included with the Clarity 3D Solver, allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB. This way  critical 3D structures that cross from the board to the connector can be modeled and optimized as one structure. Updates to the PCB can be automatically back-annotated to the PCB layout tool.

The 3D Workbench offers:

  • SI and PI applications
  • A familiar 3D look and feel
  • Ability to import mechanical structures
  • Ability to import electrical databases and merge with mechanical structures
  • 3D solid modeling (parametric and full featured)
  • Simulation of:
    • Twisted pair wiring (cables)
    • Backplane plus connectors
    • Connector modeling (HDMI, SATA, etc.)
    • SMA connector on a PCB
Rigid-Flex Support

Industry-first full Rigid-Flex PCB extraction from a single layout database provides accurate interconnect modeling of both rigid and meshed-ground flex cable zones. The zone information is automatically imported from version 17.2 of Cadence Allegro® technology.

  • Sigrity PowerSI technology
Faster IC Package Modeling

IC package modeling of designs with thousands of bumps/balls is now 3X faster and memory consumption has been reduced by 75 percent.

  • Sigrity XtractIM™ technology
Power Integrity Updates

Upgraded power integrity (PI) technology addresses new checking requirements and new usability requirements for PCB front-to-back design flows. Many enhancements have been added, including hierarchical views, quick search, and filtering, comparison tree report, and tool tips.

  • Allegro PowerTree™ technology

The DC analysis technology has been upgraded to support integration with Allegro technology, HTML block-diagram enhancements, and automated add-nodes-on-pads enhancements.

  • Sigrity PowerDC™ technology

The AC analysis technology has added some additional checks that now look at the weighted AC current and checks for equal voltage. New batch-mode “projects” allow these two new workflows as well as others to be setup as a set of batch checks.

  • Sigrity OptimizePI™ technology
Signal Integrity Updates

 

Upgraded signal integrity (SI) technology accelerates the time it takes to verify memory interfaces, serial links, and the plethora of other signals on a PCB that can cause a design to fail in the lab. The technology now features workflows and visions that can be used to quickly perform electrical rule checks that find impedance variations and excessive coupling. These checks require no models and can be run by both expert and non-experts in signal integrity.

  • Sigrity Aurora

 

Learn how to extend your PCB design and analysis beyond package and board. Sigrity 3D Workbench allows users to import mechanical structures and merge them with the PCB so critical 3D structures that cross from the board to the connector can be modeled and optimized as one structure.

Videos

Sigrity Tech Tip: How to Build an IBIS-AMI Model

DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

Sigrity Tech Tip: How PCB Designers Can Find and Fix Power Integrity Problems

Sigrity Tech Tip: How to Accurately Model a Multi-Gigabit Serial Link 10 Times Faster

SiriusXM Simulates DDR3 Interfaces with Sigrity Tools

Nexus Interposers and Cadence Tools Enhance DDRx Designs

News ReleasesVIEW ALL
  • Cadence Introduces Voltus-XP Technology with Extensive Parallelism, Up to 5X Acceleration, and Increased Capacity for Power Signoff at Advanced Nodes 07/23/2018

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces 01/19/2016

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