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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
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        • 先進製程
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        • 低功耗方案
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        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
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Allegro PSpice System Designer

Full-featured mixed-signal simulation

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Key Benefits

  • Fast, accurate analysis of analog and mixed-signal designs
  • PSpice technology at the core for fast and accurate simulations
  • Seamless integration with Allegro Design Entry HDL
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

The Cadence® Allegro® PSpice® System Designer provides complete pre- and post-layout testing for analog and mixed-signal designs with powerful simulation, debugging, design, and analysis utilities. 

With its core Cadence PSpice technology, the Allegro PSpice System Designer provides fast and accurate simulations. This advanced analysis package includes utilities for sensitivity analysis, goal-based multi-parameter optimization, component stress and reliability analysis, and Monte Carlo analysis for yield estimation. The parametric plotter analyzes interdependence among parameters and converts simulation data into meaningful results. When combined with Allegro Design Entry HDL, the schematics drawn in Allegro PSpice System Designer can also drive PCB layout, significantly reducing design time and eliminating redrawing errors. It includes a large library of known models and behavioral modeling techniques that make refining the analog/digital interface a straightforward task.

Automotive TCL1 Certified for ISO 26262

The industry’s first PCB design and verification flow to achieve “Fit for Purpose – Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The flow includes everything from design authoring to simulation to physical realization and verification using the PSpice, Allegro, and OrCAD® product suites. The high-performance design entry, simulation, and layout editing tools provide an integrated environment for design engineers to validate the safety specifications against individual circuit specifications for design confidence. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

Features

  • Performs AC, DC, noise, transient, and parameter sweep analyses
  • Includes magnetic parts editor for transformer and inductor design
  • Utilizes a large inventory of accurate internal models with temperature effects
  • Describes functional blocks using editable behavioral models
  • Includes library of more than 33,000 known devices and components
  • Provides automatic circuit optimizer to increase performance
  • Performs circuit sensitivity, component stress, and productive yield analyses
  • Interfaces with MathWorks's MATLAB and Simulink tools for advanced electrical modeling

Contact Us

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News ReleasesVIEW ALL
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Cadence and MathWorks Provide System-Level Simulation Solutions for Mixed-Signal IoT and Automotive Applications 11/03/2016

  • New Cadence Allegro Platform Accelerates Design of Compact, High-Performance Products Using Flex and Rigid-Flex Technologies 05/02/2016

  • Cadence Strengthens Allegro Technology Portfolio to Make Design Cycles Shorter and More Predictable 05/19/2015

  • Cadence Announces New Allegro TimingVision Environment to Speed Timing Closure of High-Speed PCB Interfaces by up to 67% 03/04/2014

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