Controller for PCIe | Cadence

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Overview

The Cadence^® Controller IP for PCI Express^® (PCIe^®) is architected to quickly and easily integrate into any SoC, and addresses a wide range of high-performance as well as low-power requirements for a broad spectrum of applications, including high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), supercomputing platforms, storage solutions, server applications, and mobile platforms. The controller area is optimized for each application to provide you with the best power and performance.

Controller for PCIe

Key Benefits

Mature

Compliance-proven IP, with customer SoCs in volume production over many generations

Application Optimized

IP features optimized for key verticals like storage, automotive, enterprise, and AI/ML, configured to your specific needs with minimal gate count

Ease of Use

Fully verified pre-integrated IP delivery, with firmware and testbenches for rapid bring-up

Features

The Cadence Controller IP for PCIe is compliant with PCIe 6.0, 5.0, 4.0, 3.1, 2.1, 1.1 protocol versions and supports the latest ECNs including IDE/DOE so that applications can benefit from the latest updates to the specifications
The controller IP is available as root-port, end-point, or dual-mode to allow for versatile use cases, and multifurcation support allows applications to build configurations that can support configurations from 1x16 to 16x1 easily
The controller provides SR-IOV support with 256 functions and 4K payload size, scalable I/O virtualization with PASID is also available
Benchmarked at 95% of theoretical performance, superscalar design for high throughput and low latency at all data rates, applications have a choice of client interfaces for maximum performance

Videos

Cadence Subsystem IP for PCIe® 6.0: Protocol and Electrical Testing

Cadence Subsystem IP for PCIe® 6.0: Protocol Stack Demo

Resources

video

Cadence Solutions for the Latest PCIe 6.0 and 5.0 Specifications