Overview

The Cadence® 16G Multi-Protocol PHY is a silicon-proven, high-end SerDes PHY operating at speeds from 1.25Gbps to 16Gbps. It features long-reach equalization capability at low active and standby power with low sub-states exit latency. This PHY IP is compliant with PCI Express® (PCIe®) 4.0, 10G-KR, and SGMII, and provides users with great flexibility to mix and match protocols within the same single PHY macro.

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Key Benefits

High Performance

Single macro supports max 16Gbps with up to 16 lanes for long-reach applications

Mature and Silicon-Proven

Compliance-proven customer SoCs in volume production

Low Risk

Fully validated by Cadence’s rigorous IP qualification process and system stress tests

Ease of Use

Fully verified pre-integrated IP delivery, with package and signal integrity support and firmware for rapid bring-up

Features

  • Wide range of protocols that support networking, HPC, and applications
  • Low-latency, long-reach, and low-power modes
  • Multi-Link PHY—mix protocols within the same macro
  • EyeSurf—non-destructive on-chip oscilloscope
  • Extensive set of isolation, test modes, and loop-backs including APB and JTAG
  • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
  • Selectable serial pin polarity reversal for both transmit and receive paths
16G-3D-Abstract