The Cadence® Denali® HBM2E/2 PHY and Controller IP is silicon-proven and includes architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the data bandwidth. It is engineered to quickly and easily integrate into SoCs and is verified as part of a complete memory subsystem solution. The HBM2E/2 PHY and Controller IP is an ideal solution for artificial intelligence (AI), high-performance computing (HPC), and image processing applications.


Key Benefits


Silicon characterization reports available

Low Latency

For data-intensive applications

High Performance

Increased data integrity from error correction and optimized throughput of unique pseudo-channel interleaving

Low Power and Area

Low-power control and advanced low-power modes with power down and self-refresh


  • Advanced clocking architecture minimizes clock jitter
  • DFI PHY Independent Mode for initialization and training
  • IEEE 1500 interface, Memory BIST feature, and loop-back function
  • Designed for optimized interposer routing
  • Programmable per-bit (PVT compensated) deskew on read and write datapaths
  • High-performance command queue placement and command execution selection
  • Optimized throughput of unique pseudo-channel interleaving
  • Lowest latency for data-intensive applications
  • Low-power control and advanced low-power modes with power-down and self-refresh
  • Memory controller interface is based on DFI 5.0
  • DFI frequency ratio of 2:1
  • Memory BIST feature